LMH1981

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SNLS214H – APRIL 2006 – REVISED MARCH 2013

For SDTV formats, the back porch pulse's negative-going leading edge is derived from the input's positive-going

sync edge with a propagation delay, and the pulse width spans an appropriate duration of the color burst

envelope for NTSC/PAL. During the vertical interval, its pulse width is shorter to correspond with the narrow

serration pulses. For EDTV formats, the back porch pulse behaves similar to the SDTV case except that the

shorter pulse width is always maintained. For HDTV formats, the pulse's leading edge is derived from the input's

negative-going trailing sync edge with a propagation delay, and the pulse width is even narrower to correspond

with the shortest back porch duration of HDTV formats.

Odd/Even Field Output

OEOUT (pin 14) provides an odd/even field output signal, which facilitates identification of odd and even fields for

interlaced or segmented frame (sF) formats. For interlaced or segmented frame formats, the odd/even output is

logic high during an odd field (field 1) and logic low during an even field (field 2). The odd/even output edge

transitions align with VSync's leading edge to designate the start of odd and even fields. For progressive (non-

interlaced) video formats, the output is held constantly at logic high.

Video Format Output (Lines-per-Field Data)

The LMH1981 counts the number of HSync pulses per field to approximate the total horizontal line count per field

(vertical resolution). This can be used to identify the video format and enable dynamic adjustment of video

system parameters, such as color space or scaler conversions. The line count per field is output to VFOUT (pin

9) as an 11-bit binary data stream. The video format data stream is clocked out on the 11 consecutive leading

edges of HSync, starting at the 3rd HSync after each VSync leading edge. Outside of these active 11-bits of

data, the video format output can be either 0 or 1 and should be treated as undefined. Refer to Figure 15 to see

the VFOUT data timing for the 480P progressive format and Figure 16 and Figure 17 for the 1080I interlaced

format. See Table 4 for a summary of VFOUT data for all supported formats.

A FPGA/MCU can be used to decode the 11-bit VFOUT data stream by using HSync as the clock source signal

and VSync as the enable signal. Using the FPGA's clock delay capability, a delayed clock derived from HSync

can be used as the sampling clock to latch the VFOUT data in the middle of the horizontal line period rather than

near the VFOUT data-bit transitions in order to avoid setup time requirements.

Table 4. VFOUT Data Summary(1)

TV Format

VFOUT Data

VFOUT Data

(Total Lines per Field)

Field 1

Field 2

NTSC/480I

00100000100b

00100000011b

(262.5)

260d

259d

PAL/576I

00100110110b

00100110101b

(312.5)

310d

309d

480P

01000001010b

N/A

(525)

522d

576P

01001101110b

N/A

(625)

622d

720P

01011101011b

N/A

(750)

747d

1080I

01000110000b

01000101111b

(562.5)

560d

559d

1080P

10001100010b

N/A

(1125)

1122d

(1)

Note: VFOUT Data has an average offset of

−3 lines due to the HSync pulses uncounted during the VSync pulse interval.

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