1/fS

32/fS

NORMAL DATA

ZERO DATA

UNDEFINED

DATA

NORMAL DATA

SYNCHRONOUS

ASYNCHRONOUS

SYNCHRONOUS

Resynchronization

Synchronization Lost

DOUT

State of Synchronization

T0020-05

21

PCM1802

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SLES023D – DECEMBER 2001 – REVISED DECEMBER 2016

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Figure 27 illustrates the digital output response for loss of synchronization and resynchronization. During

undefined data, some noise might be generated in the audio signal. The transition of normal to undefined data

and undefined or zero data to normal creates a data discontinuity in the digital output, which generates some

noise in the audio signal.

TI recommends setting PDWN low to achieve stable analog performance when the sampling rate, interface

mode, data format, or oversampling control is changed.

Figure 27. ADC Digital Output for Loss of Synchronization and Resynchronization

7.4.3 Master Mode

In master mode, BCK, LRCK, and FSYNC work as output pins, and these pins are controlled by timing which is

generated in the clock circuit of the PCM1802. FSYNC is used to designate the valid data from the PCM1802.

The rising edge of FSYNC indicates the starting point of the converted audio data and the falling edge of this

signal indicates the ending point of the data. The frequency of this signal is fixed at 2 × LRCK. The duty cycle

ratio depends on data bit length. The frequency of BCK is fixed at 64 × LRCK. The 768-fS system clock is not

available in master mode.

7.4.4 Slave Mode

In slave mode, BCK, LRCK, and FSYNC work as input pins. FSYNC enables the BCK signal, and the device can

shift out the converted data while FSYNC is HIGH. The PCM1802 accepts the 64-fS BCK or the 48-fS BCK

format. The delay of FSYNC from the LRCK transition must be within 16 BCKs for the 64-fS BCK format and

within 12 BCKs for the 48-fS BCK format.

7.4.5 Interface Mode

The PCM1802 supports master mode and slave mode as interface modes, and they are selected by MODE1 and

MODE0 as shown in Table 9.

In master mode, the PCM1802 provides the timing for serial audio data communications between the PCM1802

and the digital audio processor or external circuit. In slave mode, the PCM1802 receives the timing for data

transfer from an external controller.

Table 9. Interface Mode

MODE1

MODE0

INTERFACE MODE

0

0

Slave mode (256 fS, 384 fS, 512 fS, 768 fS)

0

1

Master mode (512 fS)

1

0

Master mode (384 fS)

1

1

Master mode (256 fS)