TMS320VC33 datasheet(24/53 Pages) TI2

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EXTCLK

RESET (1)(3)

IACK

D[31:0]

PAGEx, A[23:0]

STRB

Asynchronous

Reset Signals (2)

R/ W

Ten H1 Clock Cycles

tsu(RESET-EXTCLKL)

td(EXTCLKH-H1H)

t d(EXTCLKH-H1L)

t d(EXTCLKH-H3L)

tsu(RESETH-H1L)

tdis(H1H-DZ)

td(EXTCLKH-H3H)

td(H3H-CONTROLH)

tdis(H3H-AZ)

td(H1H-RWH)

td(H1H-IACKH)

t dis(RESETL-ASYNCH)

Execution of

Load of IOF

I /OxFx Bit (1)

XFx

td(H3H-XF)

SM320VC33, SMJ320VC33

SGUS034F – FEBRUARY 2001 – REVISED JUNE 2015

www.ti.com

Parameter Measurement Information (continued)

I/OxFx represents either bit 1 or bit 5 of the IOF register.

Figure 13. Timing for Changing XFx from Input to Output Mode

Clock circuit is configured in C31-compatible divide-by-2 mode. If configured for x1 mode, EXTCLK directly

drives H3.

Asynchronous reset signals include XF0/1, CLKX0, DX0, FSX0, CLKR0, DR0, FSR0, and TCLK0/1.

RESET is a synchronous input that can be asserted at any point during a clock cycle. If the specified timings are

met, the exact sequence shown occurs; otherwise, an additional delay of one clock cycle is possible.

In microprocessor mode, the reset vector is fetched twice, with seven software wait states each time. In

microcomputer mode, the reset vector is fetched twice, with no software wait states.

The address and PAGE3 to PAGE0 outputs are placed in a high-impedance state during reset requiring a nominal

10- to 22-k

Ω pullup. If not, undesirable spurious reads can occur when these outputs are not driven.

Figure 14. RESET Timing

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