8 Detailed Description

8.1 Reference

The SN74HCS157 is a high speed silicon gate CMOS multiplexer well suited to multiplexing and data routing

applications. It contains four 2:1 multiplexers.

The SN74HCS157 operates asynchronously, with each Y output being equal to the input selected by the

address input (A/B). All four channels are controlled by the same address input.

The strobe (G) input forces all Y outputs low, regardless of the state of other inputs.

All inputs include Schmitt-triggers allowing for slow input transitions and providing additional noise margin.

8.2 Functional Block Diagram

A/B

xA

xB

xY

G

Shared Control Logic

One of Four 2:1 Multiplexers

Figure 8-1. Logic Diagram (Positive Logic) for SN74HCS157

8.3 Feature Description

8.3.1 Balanced CMOS Push-Pull Outputs

This device includes balanced CMOS push-pull outputs. The term "balanced" indicates that the device can sink

and source similar currents. The drive capability of this device may create fast edges into light loads so routing

and load conditions should be considered to prevent ringing. Additionally, the outputs of this device are capable

of driving larger currents than the device can sustain without being damaged. It is important for the output power

of the device to be limited to avoid damage due to overcurrent. The electrical and thermal limits defined in the

Absolute Maximum Ratings must be followed at all times.

Unused push-pull CMOS outputs should be left disconnected.

8.3.2 CMOS Schmitt-Trigger Inputs

This device includes inputs with the Schmitt-trigger architecture. These inputs are high impedance and are

typically modeled as a resistor in parallel with the input capacitance given in the Electrical Characteristics table

from the input to ground. The worst case resistance is calculated with the maximum input voltage, given in the

Absolute Maximum Ratings table, and the maximum input leakage current, given in the Electrical Characteristics

table, using Ohm's law (R = V ÷ I).

The Schmitt-trigger input architecture provides hysteresis as defined by ΔVT in the Electrical Characteristics

table, which makes this device extremely tolerant to slow or noisy inputs. While the inputs can be driven much

slower than standard CMOS inputs, it is still recommended to properly terminate unused inputs. Driving the

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SN74HCS157

SCLS847 – SEPTEMBER 2020

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Product Folder Links: SN74HCS157