Right-Justified

23

22

SCLK

32Clks

LRCLK

LeftChannel

24-BitMode

1

20-BitMode

16-BitMode

15

14

MSB

LSB

SCLK

32Clks

RightChannel

2-ChannelRight-Justified(SonyFormat)StereoInput

T0034-03

19

18

1

19

18

1

0

0

0

15

14

15

14

23

22

1

15

14

MSB

LSB

19

18

1

19

18

1

0

0

0

15

14

15

14

TAS5086

www.ti.com ................................................................................................................................................... SLES131C – FEBRUARY 2005 – REVISED JUNE 2008

Right-justified (RJ) timing uses LRCLK to define when the data being transmitted is for the left channel and when

it is for the right channel. LRCLK is high for the left channel and low for the right channel. A bit clock running at

64 fS is used to clock in the data. The first bit of data appears on the data 8 bit-clock periods (for 24-bit data)

after LRCLK toggles. In RJ mode, the LSB of data always is clocked by the last bit clock before LRCLK

transitions. The data is written MSB-first and is valid on the rising edge of bit clock. The TAS5086 masks unused

leading data bit positions.

Figure 20. Right-Justified 64-fS Format

Copyright © 2005–2008, Texas Instruments Incorporated

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