TLK1221

www.ti.com....................................................................................................................................... SLLS713C – FEBRUARY 2007 – REVISED SEPTEMBER 2009

Table 2. PIN FUNCTIONS (continued)

PIN

I/O

DESCRIPTION

NAME

NO.

RXP

34

PECL

Differential input receive. RXP and RXN together are the differential serial input interface

RXN

33

I

from a copper or an optical I/F module.

Reference clock. REFCLK is an external input clock that synchronizes the receiver and

transmitter interface (60 MHz to 130 MHz). The transmitter uses this clock to register the

REFCLK

14

I

input data (TD0–TD9) for serialization.

In the TBI mode that data is registered on the rising edge of REFCLK.

Transmit data. These inputs carry 10-bit parallel data output from a protocol device to the

transceiver for serialization and transmission. This 10-bit parallel data is clocked into the

TD0–TD9

2–5, 7–12

I

transceiver on the rising edge of REFCLK and transmitted as a serial stream with TD0 sent

as the first bit.

Receive data. These outputs carry 10-bit parallel data output from the transceiver to the

RD0–RD9

29–27, 25–19

O

protocol layer. The data is referenced to terminals RBC0 and RBC1. RD0 is the first bit

received.

Receive byte clock. RBC0 and RBC1 are recovered clocks used for synchronizing the 10-bit

output data on RD0–RD9.

In the half-rate mode, the 10-bit output data words are valid on the rising edges of RBC0 and

RBC0

17

RBC1. These clocks are adjusted to half-word boundaries in conjunction with synchronous

O

RBC1

18

detect. The clocks are always expanded during data realignment and never slivered or

truncated. RBC0 registers bytes 1 and 3 of received data. RBC1 registers bytes 0 and 2 of

received data. In normal-rate mode, only RBC0 is valid and operates at 1/10th the serial data

rate. Data is aligned to the rising edge.

Receive clock mode select. When RBCMODE is low, half-rate clocks are output on RBC0

I

RBCMODE

13

and RBC1. When RBCMODE is high, a full baud-rate clock is output on RBC0, and RBC1 is

P/D(1)

held low.

Synchronous function enable. When SYNCEN is high, the internal synchronization function is

I

activated. When this function is activated, the transceiver detects the comma pattern

SYNCEN

32

P/U (2)

(0011 111 negative beginning disparity) in the serial data stream and realigns data on byte

boundaries if required. When SYNCEN is low, serial input data is unframed in RD0–RD9.

Synchronous detect. The SYNC output is asserted high upon detection of the comma pattern

in the serial data path. SYNC pulses are output only when SYNCEN is activated (asserted

SYNC/PASS

30

O

high). In PRBS test mode (PRBSEN = high), SYNC/PASS outputs the status of the PRBS

test results (high = pass).

TEST

Loop enable. When LOOPEN is high (active), the internal loopback path is activated. The

transmitted serial data is directly routed to the inputs of the receiver. This provides a self-test

I

LOOPEN

15

capability in conjunction with the protocol device. The TXP and TXN outputs are held in a

P/D(3)

high-impedance state during the loopback test. LOOPEN is held low during standard

operational state with external serial outputs and inputs active.

PRBS enable. When PRBSEN is high, the PRBS generation circuitry is enabled. The PRBS

I

verification circuit in the receive side is also enabled. A PRBS signal can be fed to the

PRBSEN

31

P/D(3)

receive inputs and checked for errors, which are reported by the SYNC/PASS terminal

indicating low.

When this terminal is low, the device is disabled for Iddq testing. RD0–RD9, RBCn, TXP and

I

ENABLE

1

TXN are high-impedance. The pullup and pulldown resistors on any input are disabled.

P/U(2)

When ENABLE is high, the device operates normally.

POWER

VDD

6, 16, 26

Supply

Digital logic power. Provides power for all digital circuitry and digital I/O buffers

Analog power. VDDA provides power for the high-speed analog circuits, receiver, and

VDDA

37

Supply

transmitter.

VDDPLL

36

Supply

PLL power. Provides power for the PLL circuitry. This terminal requires additional filtering.

GROUND

GNDA

35, 40

Ground

Analog ground. GNDA provides a ground for the high-speed analog circuits, RX and TX.

GNDQFN

PAD

Ground

Digital logic ground. Provides a ground for the logic circuits and digital I/O buffers

(1)

P/D = Internal pulldown resistor

(2)

P/U = Internal pullup resistor

(3)

P/D = Internal pulldown resistor

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