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TLV702

SLVSAG6D – SEPTEMBER 2010 – REVISED JULY 2019

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Feature Description (continued)

7.3.3 Dropout Voltage

The TLV702 uses a PMOS pass transistor to achieve low dropout. When (VIN – VOUT) is less than the dropout

voltage (VDO), the PMOS pass device is in the linear (triode) region of operation and the input-to-output

resistance is the RDS(on) of the PMOS pass element. VDO scales approximately with output current because the

PMOS device behaves as a resistor in dropout.

As with any linear regulator, PSRR and transient response are degraded as (VIN – VOUT) approaches dropout.

This effect is shown in Figure 13.

7.3.4 Undervoltage Lockout

The TLV702 uses a UVLO circuit to keep the output shut off until internal circuitry is operating properly.

7.4 Device Functional Modes

7.4.1 Normal Operation

The device regulates to the nominal output voltage under the following conditions:

•

The input voltage is greater than the nominal output voltage added to the dropout voltage.

•

The output current is less than the current limit.

•

The input voltage is greater than the UVLO voltage.

7.4.2 Dropout Operation

If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other

conditions are met for normal operation, the device operates in dropout mode. In this condition, the output

voltage is the same as the input voltage minus the dropout voltage. The transient performance of the device is

significantly degraded because the pass device is in a triode state and no longer regulates the output voltage of

the LDO. Line or load transients in dropout may result in large output voltage deviations.

Table 1 lists the conditions that lead to the different modes of operation.

Table 1. Device Functional Mode Comparison

OPERATING MODE

PARAMETER

VIN

IOUT

Normal mode

VIN > VOUT (nom) + VDO

IOUT < ICL

Dropout mode

VIN < VOUT (nom) + VDO

IOUT < ICL

Current limit

VIN > UVLO

IOUT > ICL