PL133-47

Low-Power 2.25V to 3.63V DC to 150MHz 1:4 Fanout Buffer IC

Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 1/27/11 Page 4

SWITCHING CHARACTERISTICS (Commercial and Industrial Temperature D evices)

[3 ]

Parameter

Description

Test Conditions

Min.

Typ.

Max.

Unit

Duty Cycle [2] = t2 ÷ t1

Measured at 1.4V, Input is 50%

40

50

60

%

t3

Rise Time [2]

Measured between 0.8V and 2.0V

–

–

1.5

ns

t4

Fall Time [2]

Measured between 0.8V and 2.0V

–

–

1.5

ns

t5

Output to Output Skew [2]

All outputs equally loaded

–

–

250

ps

t6

Propagation Delay, REF Rising

Edge to CLKX Rising Edge [2]

Measured at VDD/2

1

5

9.2

ns

Notes:

1. REF input has a threshold voltage of VDD/2

2. Parameter is guaranteed by design and characterization. Not 100% tested in produ ction.

3. All parameters are specified with loaded outputs.

NOISE CHARACTERISTICS (Commercial and Industrial Temperature D evices)

Parameter

Description

Test Conditions

Min.

Typ.

Max.

Unit

Additive Phase Jitter

V DD=3.3V, Frequency=100MHz

Offset=12KHz ~ 20MHz

60

fs

PL133-47 Additive Phase Jitter:

VDD=3.3V, CLK=100MHz, Integration Range 12KHz to 20MHz: 0.059ps typical.

-160

-150

-140

-130

-120

-110

-100

-90

-80

-70

-60

10

100

1000

10000

100000

1000000

10000000

100000000

Offset Frequency (Hz)

REF Input

PL133-47 Output

When a buffer is used to pass a signal then the buffer will add a little bit of its own noise. The phase noise on the output of the

buffer will be a little bit more than the phase noise in the input signal. To quantify the noise addition in the buffer we compare the

Phase Jitter numbers from the input and the output. The difference is called "Additive Phase Jitter". The formula for the Additive

Phase Jitter is as follows:

Additive Phase Jitter = (Output Phase Jitter) - (Input Phase Jitter)

2

2