PCA9544A

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© NXP Semiconductors N.V. 2014. All rights reserved.

Product data sheet

Rev. 5 — 23 April 2014

6 of 31

NXP Semiconductors

PCA9544A

4-channel I2C-bus multiplexer with interrupt logic

6.

Functional description

Refer to Figure 1 “Block diagram”.

6.1 Device addressing

Following a START condition the bus master must output the address of the slave it is

accessing. The address of the PCA9544A is shown in Figure 5. To conserve power, no

internal pull-up resistors are incorporated on the hardware selectable address pins and

they must be pulled HIGH or LOW.

The last bit of the slave address defines the operation to be performed. When set to

logic 1 a read is selected, while a logic 0 selects a write operation.

6.2 Control register

Following the successful acknowledgement of the slave address, the bus master sends a

byte to the PCA9544A which is stored in the Control register. If the PCA9544A receives

multiple bytes, it saves the last byte received. This register can be written and read via the

I2C-bus.

6.2.1 Control register definition

A SCx/SDx downstream pair, or channel, is selected by the contents of the control

register. This register is written after the PCA9544A has been addressed. The 3 LSBs of

the control byte are used to determine which channel is to be selected. When a channel is

selected, it will become active after a STOP condition has been placed on the I2C-bus.

This ensures that all SCx/SDx lines are in a HIGH state when the channel is made active,

so that no false conditions are generated at the time of connection.

Fig 5.

Slave address

002aab189

1

1

1

0

A2

A1

A0 R/W

fixed

hardware

selectable

Fig 6.

Control register

002aae297

INT3 INT2 INT1 INT0

X

B2

B1

B0

interrupt bits

(read only)

channel selection bits

(read/write)

76543210

bit

enable bit