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IP5328P 数据表(PDF) 3 Page - Injoinic Technology Co.,Ltd.

部件名 IP5328P
功能描述  Fully-Integrated Bi-directional PD3.0 and Fast Charge Power Bank SOC with Multiple Input and Output Ports
PDF  28 Pages
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制造商  INJOINIC [Injoinic Technology Co.,Ltd.]
网页  http://www.injoinic.com
标志 INJOINIC - Injoinic Technology Co.,Ltd.

IP5328P 数据表(HTML) 3 Page - Injoinic Technology Co.,Ltd.

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IP5328P
V1.2
Email: service@injoinic.com
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Copyright © 2015, Injoinic Corp.
1. Pin Definition
VING
VBUS
VBUSG
VOUT2
VOUT2G
VOUT1G
VOUT1
DMA1
DPA1
31
32
33
34
35
36
38
37
39
40
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
13
14
12
11
LIGHT
BST
LX
LX
LX
LX
L3
L2
L1
30 29 28 27 26 25 24 23 22 21
DMA2
IP5328P
QFN40
41 EPAD
LX
Figure 2 IP5328P Pin Assignments
Pin Num
Pin Name
Description
1
DPA2
DP data line on VOUT2 USB port
2
CC1
CC1 line on USB C port
3
CC2
CC2 line on USB C port
4
DMC
DM data line on USB C port
5
DPC
DP data line on USB C port
6
DMB
DM data line on Micro USB port
7
DPB
DP data line on Micro USB port
8/9/22/23
VSYS
Public Node of system input and output
10
NTC
NTC Resistor input for battery temperature sense
11
L1
Battery level display drive pin L1, reused as I2C1 SCK
12
L2
Battery level display drive pin L2, reused as I2C1SDA
13
L3
Battery level display drive pin L3, reused as VSET, used for MCU wake up
output pin during I2C1 mode
14/15/16/17/18
LX
DCDC switch node, connect to inductor
19
BST
Internal high voltage drive, serial capacitor to LX
20
LIGHT
Fast charge mode indicator
21
RSET
Battery internal resistance compensate, trimming the battery level curve,
used as MCU wake up pin during I2C2 mode
24
VSP
Positive sample node of VSYS current, separate layout with VSYS
25
VSN
Negative sample node of VYSY current



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