DIX4192IPFBRG4 datasheet(8/71 Pages) TI2

8 / 71 page

DIX4192

SBFS031F – FEBRUARY 2006 – REVISED SEPTEMBER 2016

www.ti.com

Product Folder Links: DIX4192

Submit Documentation Feedback

Timing Requirements (continued)

MIN

NOM

MAX

UNIT

(1)

All values referred to the VIH minimum and VIL maximum levels listed in the Digital I/O Characteristics section of this table.

(2)

A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIH minimum input level) to bridge the

undefined region of the falling edge of SCL.

(3)

The maximum tHDDAT has only to be met if the device does not stretch the Low period (tLOW) of the SCL signal.

(4)

A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but the requirement that tSUDAT be 250 ns (minimum)

must then be met. For the DIX4192, this condition is automatically the case, because the device does not stretch the Low period of the

SCL signal.

(5)

CB is defined as the total capacitance of one bus line in picofarads (pF). If mixed with High-Speed mode devices, faster fall times are

allowed.

tCDH

CDIN data hold time

tCFDO

CCLK falling to CDOUT data valid

tCSZ

CS rising to CDOUT high-impedance,

HOST INTERFACE: I2C STANDARD MODE(1)

fSCL

SCL clock frequency

100

kHz

tHDSTA

Hold time repeated START condition

μs

tLOW

Low period of SCL clock

4.7

μs

tHIGH

High period of SCL clock

μs

tSUSTA

Set-up time repeated START condition

4.7

μs

tHDDAT

Data hold time

0(2)

3.45(3)

μs

tSUDAT

Data set-up time

250

Rise time for both SDA and SDL

1000

Fall time for both SDA and SDL

300

tSUSTO

Set-up time for STOP condition

μs

tBUF

Bus free time between START and STOP

4.7

μs

Capacitive load for each bus line

400

VNL

Noise margin at low level (including hysteresis)

0.1 × VIO

VNH

Noise margin at high level (including hysteresis)

0.2 × VIO

HOST INTERFACE: I2C FAST MODE(1)