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LP8550TLX/NOPB 数据表(PDF) 8 Page - Texas Instruments |
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LP8550TLX/NOPB 数据表(HTML) 8 Page - Texas Instruments |
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8 / 49 page ![]() LP8550 SNVS657E – SEPTEMBER 2010 – REVISED SEPTEMBER 2014 www.ti.com 7.9 Undervoltage Protection PARAMETER TEST CONDITIONS MIN TYP MAX UNIT UVLO[1:0] = 00 Disabled UVLO[1:0] = 01, falling 2.55 2.70 2.94 UVLO[1:0] = 01, rising 2.62 2.76 3.00 VUVLO VIN UVLO threshold voltage UVLO[1:0] = 10, falling 5.11 5.40 5.68 V UVLO[1:0] = 10, rising 5.38 5.70 5.98 UVLO[1:0] = 11, falling 7.75 8.10 8.45 UVLO[1:0] = 11, rising 8.36 8.73 9.20 7.10 Logic Interface Characteristics PARAMETER TEST CONDITIONS MIN TYP MAX UNIT LOGIC INPUT EN VIL Input low level 0.4(1) V VIH Input high level 1.2(1) V II Input current -1(1) 1(1) μA LOGIC INPUT VSYNC VIL Input low level 0.4(1) V VIH Input high level 2.2(1) V II Input current –1(1) 1(1) μA fVSYNC Frequency range 58 60 55000 Hz LOGIC INPUT PWM VIL Input low level 0.4(1) V VIH Input high level 2.2(1) V II Input current –1(1) 1(1) μA LOGIC INPUTS SCL, SDA VIL Input low level 0.2xVDDIO (1) V VIH Input high level 0.8xVDDIO (1) V II Input current –1(1) 1(1) μA LOGIC OUTPUTS SDA, FAULT VOL Output low level IOUT = 3 mA (pull-up current) 0.3 0.5(1) V IL Output leakage current VOUT = 2.8 V –1(1) 1(1) μA (1) Limits apply over the full operating ambient temperature range (–30°C ≤ TA ≤ 85°C). 7.11 I 2C Serial Bus Timing Parameters (SDA, SCLK) (1) MIN MAX UNIT fCLK Clock frequency 400 kHz 1 Hold time (repeated) START condition 0.6 μs 2 Clock low time 1.3 μs 3 Clock high time 600 ns 4 Setup time for a repeated START condition 600 ns 5 Data hold time 50 ns 6 Data setup time 100 ns 7 Rise time of SDA and SCL 20+0.1Cb 300 ns 8 Fall time of SDA and SCL 15+0.1Cb 300 ns 9 Setup time for STOP condition 600 ns 10 Bus free time between a STOP and a START condition 1.3 μs (1) Specified by design. Not production tested. VDDIO = 1.65 V to 5.5 V. 8 Submit Documentation Feedback Copyright © 2010–2014, Texas Instruments Incorporated Product Folder Links: LP8550 |
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