TEST CIRCUIT

50 W

Generator

(see Note B)

3 V or 0 V

3 V or 0 V

FORCEON

FORCEOFF

NOTES: A. CL includes probe and jig capacitance.

B. The pulse generator has the following characteristics: ZO = 50 W, 50% duty cycle, tr ≤10 ns, tf ≤10 ns.

C. tPLZ and tPHZ are the same as tdis.

D. tPZL and tPZH are the same as ten.

RL

S1

VCC

GND

CL

(see Note A)

Output

VOLTAGE WAVEFORMS

Output

VOL

VOH

tPZH

(S1 at GND)

3 V

0 V

0.3 V

Output

Input

0.3 V

1.5 V

1.5 V

50%

tPHZ

(S1 at GND)

tPLZ

(S1 at VCC)

50%

tPZL

(S1 at VCC)

Figure 6-4. Receiver Enable and Disable Times

TEST CIRCUIT

VOLTAGE WAVEFORMS

50 W

3 V

2.7 V

−2.7 V

INVALID

Output

Receiver

Input

Generator

(see Note B)

FORCEOFF

tvalid

ROUT

FORCEON

Auto-

powerdown

INVALID

DOUT

0 V

0 V

−3 V

DIN

CL = 30 pF

(see Note A)

VCC

0 V

2.7 V

−2.7 V

0.3 V

−0.3 V

0 V

Valid RS-232 Level, INVALID High

Indeterminate

Indeterminate

If Signal Remains Within This Region

For More Than 30 ms, INVALID Is Low (see Note C)

Valid RS-232 Level, INVALID High

≈V+

0 V

≈V−

V+

VCC

ten

V−

NOTES: A. CL includes probe and jig capacitance.

B. The pulse generator has the following characteristics: PRR = 5 kbit/s, ZO = 50 W, 50% duty cycle, tr ≤10 ns, tf ≤10 ns.

C. Auto-powerdown disables drivers and reduces supply current to 1 mA.

50% VCC

50% VCC

2.7 V

−2.7 V

0.3 V

0.3 V

tinvalid

Supply

Voltages

Figure 6-5. INVALID Propagation Delay Times and Supply Enabling Time

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MAX3243

SLLS350Q – APRIL 1999 – REVISED AUGUST 2024

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