PM8800

Pins description and connection diagrams

5/10

6

AUXI_IRL

In-rush current limit and auxiliary source enable pin.

Pulling up this pin to the auxiliary source will change the internal UVLO

settings and allow PD to be powered with voltage lower than nominal

PoE voltages. In this condition inrush current limit is set to default val-

ues. A resistance between this pin and VSS will set the level of inrush

current limit.

7

DCCL

DC Current Limit.

A resistor between DCCL and VSS will set the current limit for the inter-

face section of the PM8800. It can be set to exceed the IEEE802.3af

current limit . Leave the pin open for standard IEEE 802.3af applica-

tions

8

VSS

System low potential input.

9GND

System return for the PWM converter.

It is the drain of the internal hot-swap power MOSFET.

10

GD

Output of the PWM controller. External power MOSFET gate driver out-

put

11

VCC

Output of the internal high voltage regulator.

When the auxiliary transformer winding (if used) raises the voltage on

this pin above the regulation set point, the internal regulator will be

shutdown, reducing the controller power dissipation

12

nPGD

PowerGood, active low

A high to low transition indicates that handshake with the PSE has

been successfully terminated and the SMPS portion of the PM8800 can

be activated

13

CS

Current sense input.

Current sense input for current mode control and over-current protec-

tion. Current limiting is obtained with a dedicated current sense com-

parator. If the CS pin voltage exceeds 0.5V the GD pin switches low for

cycle-by-cycle current limiting. Leading edge blanking is implemented

to mask current spikes.

14

COMP

The output of the error amplifier and input of the Pulse Width Modula-

tor.COMP pull-up is provided by an internal 2.5k

Ω resistor which may

be used to bias an opto-coupler transistor.

15

VFB

Feedback signal.

Inverting input of the internal error amplifier. The non-inverting input is

internally connected to a 1.25V reference.

16

AGND

Analog PWM supply return.

GND for sensitive analog circuitry including the SMPS current limit cir-

cuitry. Must be connected to GND to improve noise immunity.

EP

Exposed Pad.

Connect this to a board plane to improve heat dissipation; must be

electrically connected to VSS

Table 1.

Pin description (continued)

Pin n

Name

Function