DC and AC parameters

M24M01-R

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Table 12.

AC characteristics at 1 MHz (preliminary data)

Test conditions specified in Table 7

Symbol

Alt.

Parameter

Min.

Max.

Unit

Clock frequency

0

1

MHz

Clock pulse width high

300

-

ns

Clock pulse width low

400

-

ns

(1)

1.

Values recommended by the I²C-bus Fast-Mode specification.

Input signal rise time

20

300

ns

(1)

Input signal fall time

20

300

ns

(2)

2.

Characterized only, not tested in production.

SDA (out) fall time

20

100

ns

Data in setup time

80

-

ns

0

-

ns

Data out hold time

50

-

ns

(3)(4)

3.

To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and the falling or

rising edge of SDA.

4.

Clock low to next data valid (access time)

50

500

ns

(5)

5.

For a reStart condition, or following a Write cycle.

Start condition setup time

250

-

ns

250

-

ns

250

-

ns

Time between Stop condition and next

Start condition

500

-

ns

Write time

-

5

ms

tNS

(2)

Pulse width ignored (input filter on SCL

and SDA)

-50

ns