CD54HC4046AF datasheet(4/28 Pages) TI

4 / 28 page

The frequency capture range (2fC) is deﬁned as the

frequency range of input signals on which the PLL will lock if

it was initially out-of-lock. The frequency lock range (2fL)is

deﬁned as the frequency range of input signals on which the

loop will stay locked if it was initially in lock. The capture

range is smaller or equal to the lock range.

With PC1, the capture range depends on the low-pass ﬁlter

characteristics and can be made as large as the lock range.

This conﬁguration retains lock behavior even with very noisy

input signals. Typical of this type of phase comparator is that

it can lock to input frequencies close to the harmonics of the

VCO center frequency.

Phase Comparator 2 (PC2)

This is a positive edge-triggered phase and frequency

detector. When the PLL is using this comparator, the loop

is controlled by positive signal transitions and the duty

factors of SIGIN and COMPIN are not important. PC2

comprises two D-type ﬂip-ﬂops, control-gating and a three-

state output stage. The circuit functions as an up-down

counter (Figure 1) where SIGIN causes an up-count and

COMPIN a down-count. The transfer function of PC2,

assuming ripple (fr = fi) is suppressed, is:

VDEMOUT =(VCC/4π)(φSIGIN - φCOMPIN) where

VDEMOUT is the demodulator output at pin 10;

VDEMOUT =VPC2OUT (via low-pass ﬁlter).

The average output voltage from PC2, fed to the VCO via the

low-pass ﬁlter and seen at the demodulator output at pin 10

(VDEMOUT), is the resultant of the phase differences of

SIGIN and COMPIN as shown in Figure 4. Typical waveforms

for the PC2 loop locked at fo are shown in Figure 5.

When the frequencies of SIGIN and COMPIN are equal but

the phase of SIGIN leads that of COMPIN, the p-type output

driver at PC2OUT is held “ON” for a time corresponding to

the phase difference (

φDEMOUT). When the phase of SIGIN

lags that of COMPIN, the n-type driver is held “ON”.

When the frequency of SIGIN is higher than that of

COMPIN, the p-type output driver is held “ON” for most of

the input signal cycle time, and for the remainder of the

cycle both n- and p-type drivers are “OFF” (three-state). If

the SIGIN frequency is lower than the COMPIN frequency,

then it is the n-type driver that is held “ON” for most of the

cycle. Subsequently, the voltage at the capacitor (C2) of

the low-pass ﬁlter connected to PC2OUT varies until the

signal and comparator inputs are equal in both phase and

FIGURE 2. PHASE COMPARATOR 1: AVERAGE OUTPUT

VOLTAGE vs INPUT PHASE DIFFERENCE:

VDEMOUT = VPC1OUT = (VCC/π) (φSIGIN -

φCOMPIN); φDEMOUT =(φSIGIN - φCOMPIN)

VCC

VDEMOUT (AV)

1/2 VCC

90o

DEMOUT

180o

FIGURE 3. TYPICAL WAVEFORMS FOR PLL USING PHASE

COMPARATOR 1, LOOP LOCKED AT fo

SIGIN

COMPIN

VCOOUT

PC1OUT

VCOIN

VCC

GND

FIGURE 4. PHASE COMPARATOR 2: AVERAGE OUTPUT

VOLTAGE vs INPUT PHASE DIFFERENCE:

VDEMOUT = VPC2OUT

= (VCC/4π) (φSIGIN - φCOMPIN);

φDEMOUT =(φSIGIN - φCOMPIN)

VCC

VDEMOUT (AV)

1/2 VCC

-360o

DEMOUT

360o

FIGURE 5. TYPICAL WAVEFORMS FOR PLL USING PHASE

COMPARATOR 2, LOOP LOCKED AT fo

SIGIN

COMPIN

VCOOUT

PC2OUT

VCOIN

VCC

GND

PCPOUT

HIGH IMPEDANCE OFF - STATE

CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A

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