SN54ACT563, SN74ACT563

OCTAL D-TYPE TRANSPARENT LATCHES

WITH 3-STATE OUTPUTS

SCAS550B – NOVEMBER 1995 – REVISED OCTOBER 2002

1

POST OFFICE BOX 655303

Directly

PCB Layout

description/ordering information

The

’ACT563

devices

are

octal

D-type

transparent latches with 3-state outputs. When

the latch-enable (LE) input is high, the Q outputs

are set to the complements of the data (D) inputs.

When LE is taken low, the Q outputs are latched

at the inverse logic levels set up at the D inputs.

A buffered output-enable (OE) input places the

eight outputs in either a normal logic state (high or

low logic levels) or the high-impedance state. In

the high-impedance state, the outputs neither

load nor drive the bus lines significantly. The

high-impedance state and increased high logic

level provide the capability to drive bus lines

without interface or pullup components.

OE does not affect internal operations of the

latches. Old data can be retained or new data can

be entered while the outputs are in the

high-impedance state.

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

ORDERING INFORMATION

TA

PACKAGE†

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

PDIP – N

Tube

SN74ACT563N

SN74ACT563N

SOIC

DW

Tube

SN74ACT563DW

ACT563

40

°Cto85°C

SOIC – DW

Tape and reel

SN74ACT563DWR

ACT563

–40

°C to 85°C

SOP – NS

Tape and reel

SN74ACT563NSR

ACT563

SSOP – DB

Tape and reel

SN74ACT563DBR

AD563

TSSOP – PW

Tape and reel

SN74ACT563PWR

AD563

CDIP – J

Tube

SNJ54ACT5634J

SNJ54ACT563J

–55

°C to 125°C

CFP – W

Tube

SNJ54ACT563W

SNJ54ACT563W

LCCC – FK

Tube

SNJ54ACT563FK

SNJ54ACT563FK

† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are

available at www.ti.com/sc/package.

1

2

3

4

5

6

7

8

9

10

20

19

18

17

16

15

14

13

12

11

OE

1D

2D

3D

4D

5D

6D

7D

8D

GND

1Q

2Q

3Q

4Q

5Q

6Q

7Q

8Q

LE

SN54ACT563 ...J OR W PACKAGE

SN74ACT563 . . . DB, DW, N, NS, OR PW PACKAGE

(TOP VIEW)

3

2

1 20 19

910 11 12 13

4

5

6

7

8

18

17

16

15

14

2Q

3Q

4Q

5Q

6Q

3D

4D

5D

6D

7D

SN54ACT563 . . . FK PACKAGE

(TOP VIEW)

UNLESS OTHERWISE NOTED this document contains PRODUCTION

DATA information current as of publication date. Products conform to

specifications per the terms of Texas Instruments standard warranty.

Production processing does not necessarily include testing of all

parameters.

Copyright

 2002, Texas Instruments Incorporated

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.