www.ti.com

DRDY

SYNC

DOUT[15:0]

t

9

t

10

t

11

CLK

ValidData

ADS1610

SBAS344C – AUGUST 2005 – REVISED OCTOBER 2006

Figure 3. Reset Timing

Timing Specifications(1)

DESCRIPTION

MIN

TYP MAX

UNIT

t1

CLK period (1/fCLK)

16.667

ns

1/t1 fCLK

1

60

MHz

t2

CLK pulse width, high or low

45%

55%

ns

t3

CLK to DRDY high (propagation delay)

12

ns

t4

DRDY pulse width, high or low

3 t1

ns

t5

Previous data valid (hold time)

0

ns

t6

New data valid (setup time)

5

ns

t7

RD and/or CS inactive (high) to DOUT high impedance

15

ns

t8

RD and/or CS active (low) to DOUT active

15

ns

t9

Delay from SYNC active (low) to all-zero DOUT[15:0]

12

ns

t10

Delay from SYNC inactive (high) to non-zero DOUT[15:0]

21

DRDY

t11

Delay from SYNC inactive (high )to valid DOUT[15:0] (time – 55 DRDY cycles; required for digital

55

DRDY

filter to settle).

(1)

Output load = 10pF|| 500k

Ω.

7

Submit Documentation Feedback