TIMING REQUIREMENTS (see Figure 21)

ADS7883

SLAS594 – JULY 2008 ....................................................................................................................................................................................................... www.ti.com

ELECTRICAL SPECIFICATIONS (continued)

VDD = 2.7 V to 5.5 V, TA = –40°C to 125°C, fsample = 2 MSPS for VDD = 2.7 V to 4.5 V, fsample = 3 MSPS for VDD = 4.5 V to 5.5

V

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

At VDD = 3 V, 2-MSPS throughput

2.15

3

At VDD = 3 V, Static state

1.8

Supply current (normal mode)

mA

At VDD = 5 V, 3-MSPS throughput

2.7

4

At VDD = 5 V, Static state

2

SCLK off

1

Power-down state supply current

µA

SCLK on (48 MHz)

90

250

VDD = 5 V, 3 MSPS

13.5

20

Power dissipation

mW

VDD = 3 V, 2 MSPS

6.45

VDD = 5 V

10

12.5

Power dissipation in static state

mW

VDD = 3 V

5.4

Power-down time

0.1

µs

Power-up time

0.8

µs

TEMPERATURE RANGE

Specified performance

–40

125

°C

All specifications typical at TA = –40°C to 125°C, VDD = 2.7 V to 5.5 V, unless otherwise specified.

PARAMETER

TEST CONDITIONS(1)

MIN

TYP

MAX

UNIT

VDD = 3 V

13.5 × tSCLK

tconv

Conversion time

ns

VDD = 5 V

13.5 × tSCLK

VDD = 3 V

78

tacq

Aquisition time

ns

VDD = 5 V

52

VDD = 3 V

10

Minimum quiet time needed from bus 3-state to start

tq

ns

of next conversion

VDD = 5 V

10

VDD = 3 V

9

15

td1

Delay time, CS low to first data (0) out

ns

VDD = 5 V

8

11

VDD = 3 V

7

tsu1

Setup time, CS low to SCLK low

ns

VDD = 5 V

5

VDD = 3 V

11

20

td2

Delay time, SCLK falling to SDO

ns

VDD = 5 V

9

12

VDD < 3 V

5.5

th1

Hold time, SCLK falling to data valid(2)

ns

VDD > 5 V

4

VDD = 3 V

9

15

td3

Delay time, 16th SCLK falling edge to SDO 3-state

ns

VDD = 5 V

8

11

VDD = 3 V

10

tw1

Pulse duration, CS

ns

VDD = 5 V

10

VDD = 3 V

9

15

td4

Delay time, CS high to SDO 3-state,

ns

VDD = 5 V

8

11

VDD = 3 V

0.45 × tSCLK

twH

Pulse duration, SCLK high

ns

VDD = 5 V

0.45 × tSCLK

VDD = 3 V

0.45 × tSCLK

twL

Pulse duration, SCLK low

ns

VDD = 5 V

0.45 × tSCLK

(1)

3-V Specifications apply from 2.7 V to 3.6 V, and 5-V specifications apply from 4.5 V to 5.5 V.

(2)

With 10-pf load.

4

Submit Documentation Feedback

Copyright © 2008, Texas Instruments Incorporated

Product Folder Link(s): ADS7883