CDCE925PW.B datasheet(8/40 Pages) TI2

8 / 40 page

CDCE925, CDCEL925

SCAS847I – JULY 2007 – REVISED OCTOBER 2016

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Product Folder Links: CDCE925 CDCEL925

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Electrical Characteristics (continued)

over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP(1)

MAX

UNIT

(6)

SDA and SCL pins are 3.3-V tolerant.

tjit(cc)

Cycle-to-cycle jitter (2) (3)

1 PLL switching, Y2-to-Y3

110

2 PLL switching, Y2-to-Y5

130

200

tjit(per)

Peak-to-peak period jitter (3)

1 PLL switching, Y2-to-Y3

100

130

2 PLL switching, Y2-to-Y5

150

220

tsk(o)

Output skew (4)

fOUT = 50 MHz, Y1-to-Y3

fOUT = 50 MHz, Y2-to-Y5

110

odc

Output duty cycle (5)

fVCO = 100 MHz, Pdiv = 1

45%

55%

SDA AND SCL

VIK

SCL and SDA input clamp voltage

VDD = 1.7 V, II = –18 mA

–1.2

IIH

SCL and SDA input current

VI = VDD, VDD = 1.9 V

±10

µA

VIH

SDA/SCL input high voltage(6)

0.7 × VDD

VIL

SDA/SCL input low voltage(6)

0.3 × VDD

VOL

SDA low-level output voltage

IOL = 3 mA, VDD = 1.7 V

0.2 × VDD

SCL/SDA Input capacitance

VI = 0 V or VDD

7.6 EEPROM Specification

MIN

TYP

MAX

UNIT

EEcyc

Programming cycles of EEPROM

100

1000

cycles

EEret

Data retention

years

7.7 Timing Requirements: CLK_IN

over operating free-air temperature range (unless otherwise noted)

MIN

NOM

MAX

UNIT

fCLK

LVCMOS clock input frequency

PLL bypass mode

160

MHz

PLL mode

160

tr / tf

Rise and fall time CLK signal (20% to 80%)

dutyCLK

Duty cycle CLK at VDD / 2

40%

60%

7.8 Timing Requirements: SDA/SCL

over operating free-air temperature range (unless otherwise noted; see Figure 8)

MIN

NOM

MAX

UNIT

fSCL

SCL clock frequency

Standard mode

100

kHz

Fast mode

400

tsu(START)

START setup time (SCL high before SDA low)

Standard mode

4.7

µs

Fast mode

0.6

th(START)

START hold time (SCL low after SDA low)

Standard mode

µs

Fast mode

0.6

tw(SCLL)

SCL low-pulse duration

Standard mode

4.7

µs

Fast mode

1.3

tw(SCLH)

SCL high-pulse duration

Standard mode

µs

Fast mode

0.6

th(SDA)

SDA hold time (SDA valid after SCL low)

Standard mode

3.45

µs

Fast mode

0.9

tsu(SDA)

SDA setup time

Standard mode

250

Fast mode

100

CDCE925PW.B 数据表(PDF) 8 Page - Texas Instruments

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