DS90CF364A, DS90CF384A

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SNLS040I – JUNE 2000 – REVISED APRIL 2013

Electrical Characteristics

(1)

(continued)

Over recommended operating supply and temperature ranges unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ

Max

Units

LVDS RECEIVER DC SPECIFICATIONS

VTH

Differential Input High Threshold

V CM = +1.2V

+100

mV

VTL

Differential Input Low Threshold

−100

mV

IIN

Input Current

V IN = +2.4V, VCC = 3.6V

±10

μA

V IN = 0V, VCC = 3.6V

±10

μA

RECEIVER SUPPLY CURRENT(2)

ICCRW

Receiver Supply Current Worst Case

CL = 8 pF,

f = 32.5 MHz

49

65

mA

Worst Case Pattern,

f = 37.5 MHz

53

70

mA

DS90CF384A (Figure 3

f = 65 MHz

81

105

mA

Figure 6)

ICCRW

Receiver Supply Current Worst Case

CL = 8 pF,

f = 32.5 MHz

49

55

mA

Worst Case Pattern,

f = 37.5 MHz

53

60

mA

DS90CF364A (Figure 3

f = 65 MHz

78

90

mA

Figure 6)

ICCRG

Receiver Supply Current, 16 Grayscale

CL = 8 pF,

f = 32.5 MHz

28

45

mA

16 Grayscale Pattern,

f = 37.5 MHz

30

47

mA

(Figure 4 Figure 5 Figure 6)

f = 65 MHz

43

60

mA

ICCRZ

Receiver Supply Current

Power Down = Low

10

55

μA

Power Down

Receiver Outputs Stay Low during

Power Down Mode

(2)

Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground

unless otherwise specified (except VOD and ΔV OD).

Receiver Switching Characteristics

(1)

Over recommended operating supply and temperature ranges unless otherwise specified

Symbol

Parameter

Min

Typ

Max

Units

CLHT

CMOS/TTL Low-to-High Transition Time (Figure 6)

2

5

ns

CHLT

CMOS/TTL High-to-Low Transition Time (Figure 6)

1.8

5

ns

RSPos0

Receiver Input Strobe Position for Bit 0 (Figure 13,

f = 25 MHz

1.20

1.96

2.82

ns

Figure 14)

RSPos1

Receiver Input Strobe Position for Bit 1

6.91

7.67

8.53

ns

RSPos2

Receiver Input Strobe Position for Bit 2

12.62

13.38

14.24

ns

RSPos3

Receiver Input Strobe Position for Bit 3

18.33

19.09

19.95

ns

RSPos4

Receiver Input Strobe Position for Bit 4

24.04

24.80

25.66

ns

RSPos5

Receiver Input Strobe Position for Bit 5

29.75

30.51

31.37

ns

RSPos6

Receiver Input Strobe Position for Bit 6

35.46

36.22

37.08

ns

RSPos0

Receiver Input Strobe Position for Bit 0 (Figure 13,

f = 65 MHz

0.7

1.1

1.4

ns

Figure 14)

RSPos1

Receiver Input Strobe Position for Bit 1

2.9

3.3

3.6

ns

RSPos2

Receiver Input Strobe Position for Bit 2

5.1

5.5

5.8

ns

RSPos3

Receiver Input Strobe Position for Bit 3

7.3

7.7

8.0

ns

RSPos4

Receiver Input Strobe Position for Bit 4

9.5

9.9

10.2

ns

RSPos5

Receiver Input Strobe Position for Bit 5

11.7

12.1

12.4

ns

RSPos6

Receiver Input Strobe Position for Bit 6

13.9

14.3

14.6

ns

RSKM

RxIN Skew Margin (2) (Figure 15)

f = 25 MHz

750

ps

f = 65 MHz

500

ps

(1)

Typical values are given for VCC = 3.3V and TA = +25C.

(2)

Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account the

DS90C383B transmitter pulse positions (min and max) and the receiver input setup and hold time (internal data sampling window -

RSPos). The RSKM will change when different transmitters are used. This margin allows for LVDS interconnect skew, inter-symbol

interference (both dependent on type/length of cable), and clock jitter (less than 250 ps).

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