Clock management

ST7580

22/33

DocID022644 Rev 2

7

Clock management

The main clock source is an 8 MHz crystal connected to the internal oscillator through the

XIN and XOUT pins. Both XIN and XOUT pins have a 32 pF integrated capacitor, in order to

drive a crystal having a load capacitance of 16 pF with no additional components.

Alternatively, an 8 MHz external clock can be directly supplied to the XIN pin, leaving XOUT

floating.

A PLL internally connected to the output of the oscillator generates the fCLK_PHY, required by

the PHY processor block engine. fCLK_PHY is then divided by two to obtain fCLK_PROTOCOL,

required by the protocol controller.

8

Functional overview

The ST7580 provides a complete physical layer (PHY) to the external host and some data

link layer (DL) services for power line communication. It is mainly developed for smart

metering applications in CENELEC A band, but suitable also for other command and control

applications and remote load management in CENELEC B and D band.

A UART host interface is available for communication with an external host, exporting all the

functions and services required to configure and control the device and its protocol stack.

The embedded PHY layer, hosted in the PHY processor, implements two different

modulation schemes: a B-FSK modulation up to 9.6 kbps and a multi-mode PSK modulation

with channel quality estimation, dual channel receiving mode, and convolutional coding,

delivering a throughput up to 28.8 kbps.

The embedded DL layer hosted in the protocol controller offers framing and error correction

services.