5.8 SMBus Digital Switching Characteristics

Unless otherwise noted, these specifications apply for VDD = +3.0 VDC to +3.6 VDC, CL (load capacitance) on output lines

= 80 pF. Boldface limits apply for TA = TJ; TMIN ≤ TA ≤ TMAX; all other limits TA = TJ = +25°C, unless otherwise noted.

The switching characteristics of the LM64 fully meet or exceed the published specifications of the SMBus version 2.0. The

following parameters are the timing relationships between SMBCLK and SMBDAT signals related to the LM64. They adhere

to but are not necessarily the same as the SMBus bus specifications.

Symbol

Parameter

Conditions

Limits

(1)

Units

(Limit)

fSMB

SMBus Clock Frequency

10

100

kHz (min)

kHz (max)

tLOW

SMBus Clock Low Time

From VIN(0) max to VIN(0) max

4.7

µs (min)

tHIGH

SMBus Clock High Time

From VIN(1) min to VIN(1) min

4.0

50

µs (min)

µs (max)

tR

SMBus Rise Time

See (2)

1

µs (max)

tF

SMBus Fall Time

See (3)

0.3

µs (max)

tOF

Output Fall Time

CL = 400 pF, IO = 3 mA

250

ns (max)

tTIMEOUT

SMBData and SMBCLK Time Low for Reset of

Serial Interface See (4)

25

35

ms (min)

ms (max)

tSU:DAT

Data In Setup Time to SMBCLK High

250

ns (min)

tHD:DAT

Data Out Hold Time after SMBCLK Low

300

930

ns (min)

ns (max)

tHD:STA

Hold Time after (Repeated) Start Condition. After

this period the first clock is generated.

4.0

µs (min)

tSU:STO

Stop Condition SMBCLK High to SMBDAT Low

(Stop Condition Setup)

100

ns (min)

tSU:STA

SMBus Repeated Start-Condition Setup Time,

SMBCLK High to SMBDAT Low

4.7

µs (min)

tBUF

SMBus Free Time between Stop and Start

Conditions

4.7

µs (min)

(1)

Limits are guaranteed to TI's AOQL (Average Outgoing Quality Level).

(2)

The output rise time is measured from (VIL max - 0.15 V) to (VIH min + 0.15 V).

(3)

The output fall time is measured from (VIH min + 0.15 V) to (VIL min - 0.15 V).

(4)

Holding the SMBData and/or SMBCLK lines Low for a time interval greater than tTIMEOUT will reset the LM64’s SMBus state machine,

therefore setting SMBDAT and SMBCLK pins to a high impedance state.

VIH

VIL

SMBCLK

P

S

VIH

VIL

SMBDAT

tBUF

tHD;STA

tLOW

tR

tHD;DAT

tHIGH

tF

tSU;DAT

tSU;STA

tSU;STO

P

Figure 5-1. SMBus Timing Diagram for SMBCLK and SMBDAT Signals

LM64

SNAS207B – MAY 2004 – REVISED JANUARY 2024

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