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LP8754 数据表(PDF) 21 Page - Texas Instruments |
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LP8754 数据表(HTML) 21 Page - Texas Instruments |
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21 / 52 page  ~2 2s Time 0 HW RST by NRST OTP_MEM_READ SW RST by I2C OTP_MEM_READ tRST1 tRST2 tRST2 LP8754 www.ti.com SNVS861A – FEBRUARY 2014 – REVISED AUGUST 2014 Inductor Current Dropping to Zero in ~2 µs (All Converters, All Phases) Figure 14. Fast Power-Down Figure 15. Reset Timings SYMBOL PARAMETER LIMIT tRST1 NRST active low pulse width 1 µs min + value on DELAY_BUCK0 register. tRST2 NRST inactive or I2C reset 25 µs max event to MEMORY READ end Table 2. Hardware Reset, Power-On Reset (POR) and Software Reset: Registers After Reset SOFTWARE RESET HARDWARE RESET POWER-ON RESET HEX ADDRESS REGISTER I2C RESET NRST LOW(1) VVIOSYS LOW 0x00 VSET_B0 All bits retained All bits retained All bits cleared 0x06 FPWM All bits cleared All bits cleared All bits cleared 0x07 to 0x0C BUCK0_CTRL to BUCK5_CTRL All bits cleared All bits cleared All bits cleared 0x0D FLAGS_0 All bits retained All bits retained All bits cleared 0x0E FLAGS_1 All bits retained All bits retained All bits cleared 0x0F INT_MASK0 All bits cleared All bits cleared All bits cleared 0x10 GENERAL All bits cleared All bits cleared All bits cleared 0x11 RESET N/A All bits cleared All bits cleared 0x12 DELAY_BUCK0 All bits cleared All bits cleared All bits cleared 0x18 CHIP_ID Read Only 0x19 PFM_LEV_B0 All bits cleared All bits cleared All bits cleared 0x1F PHASE_LEV_B0 All bits cleared All bits cleared All bits cleared 0x21 SEL_I_LOAD All bits retained All bits retained All bits cleared 0x22 LOAD_CURR Read Only 0x2E INT_MASK_2 All bits cleared All bits cleared All bits cleared (1) Reset will take effect upon complete of the power-down sequence. Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback 21 Product Folder Links: LP8754 |
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