ML4800

PRODUCT SPECIFICATION

12

REV. 1.0.5 9/25/01

Leading/Trailing Modulation

Conventional Pulse Width Modulation (PWM) techniques

employ trailing edge modulation in which the switch will

turn on right after the trailing edge of the system clock. The

error amplifier output voltage is then compared with the

modulating ramp. When the modulating ramp reaches the

level of the error amplifier output voltage, the switch will be

turned OFF. When the switch is ON, the inductor current will

ramp up. The effective duty cycle of the trailing edge modu-

lation is determined during the ON time of the switch. Figure

4 shows a typical trailing edge control scheme.

In the case of leading edge modulation, the switch is turned

OFF right at the leading edge of the system clock. When the

modulating ramp reaches the level of the error amplifier out-

put voltage, the switch will be turned ON. The effective

duty-cycle of the leading edge modulation is determined dur-

ing the OFF time of the switch. Figure 5 shows a leading

edge control scheme.

One of the advantages of this control technique is that it

requires only one system clock. Switch 1 (SW1) turns off

and switch 2 (SW2) turns on at the same instant to minimize

the momentary “no-load” period, thus lowering ripple volt-

age generated by the switching action. With such synchro-

nized switching, the ripple voltage of the first stage is

reduced. Calculation and evaluation have shown that the

120Hz component of the PFC’s output ripple voltage can be

reduced by as much as 30% using this method.

Typical Applications

Figure 6 is the application circuit for a complete 100W

power factor corrected power supply, designed using the

methods and general topology detailed in Application Note

33.

Figure 5. Typical Leading Edge Control Scheme

REF

EA

–

+

–

+

OSC

DFF

R

D

Q

Q

CLK

U1

RAMP

CLK

U4

U3

C1

RL

I4

SW2

SW1

+

DC

I1

I2

I3

VIN

L1

VEAO

CMP

U2

RAMP

VEAO

TIME

VSW1

TIME