STTS75

DC and AC parameters

31/38

Figure 16.

Bus timing requirements sequence

1.

2.

Transmitter must internally provide a hold time to bridge the undefined region (300ns max) of the falling

edge of SCL.

3.

For SMBus compatibility STTS75 supports bus timeout. Holding the SDA line low for a period greater than

timeout duration will cause STTS75 to reset the SDA line to the state of serial bus communication (SDA

high).

Table 15.

AC characteristics

Sym

Min

Max

Unit

SCL clock frequency

0

400

kHz

Time the bus must be free before a new transmission can start

1.3

µs

SDA and SCL fall time

300

ns

(2)

Data hold time

0.9

µs

START condition hold time (after this period the first clock pulse is

generated)

600

ns

Clock high period

600

ns

Clock low period

1.3

µs

SDA and SCL rise time

300

ns

Data setup time

100

ns

START condition setup time (only relevant for a repeated start

condition)

600

ns

STOP condition setup time

600

ns

(3)

75

325

ns

AI00589

SDA

P

tSU:STO

tSU:STA

tHD:STA

SR

SCL

tSU:DAT

tF

tHD:DAT

tR

tHIGH

tLOW

tHD:STA

tBUF

S

P