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6.10.3 EMIFA Electrical Data/Timing

AECLKIN

TMS320DM647/TMS320DM648

Digital Media Processor

SPRS372A – MAY 2007 – REVISED JUNE 2007

Table 6-29. Timing Requirements for AECLKIN for EMIFA(1)(2) (see Figure 6-13)

-720

-900

NO.

UNIT

MIN

MAX

tc(EKI)

Cycle time, AECLKIN

6(3)

tw(EKIH)

Pulse duration, AECLKIN high

2.7

tw(EKIL)

Pulse duration, AECLKIN low

2.7

tt(EKI)

Transition time, AECLKIN

tJ(EKI)

Period Jitter, AECLKIN

0.02E(4)

(1)

The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN.

(2)

E = the EMIF input clock (AECLKIN or SYSCLK4) period in ns for EMIFA.

(3)

Minimum AECLKIN cycle times must be met, even when AECLKIN is generated by an internal clock source. Minimum AECLKIN times

are based on internal logic speed; the maximum useable speed of the EMIF may be lower due to AC timing requirements.

(4)

This timing applies only when AECLKIN is used for EMIFA.

Figure 6-13. AECLKIN Timing for EMIFA

Peripheral Information and Electrical Specifications

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