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ADC32RF44IRMPR 数据表(PDF) 32 Page - Texas Instruments |
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ADC32RF44IRMPR 数据表(HTML) 32 Page - Texas Instruments |
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32 / 135 page  IQ 2.6 GSPS N/2 ADC NCO 2, 16 Bits 2.6 GSPS IQ Data, 2.6 GSPS RX1 IQ Output GPIO SYSREF RX2 IQ Output NCO 1, 16 Bits NCO 3, 16 Bits NCO 4, 16 Bits RX1 Real Output Wideband IQ Output 2,3 Wideband Real Output RX2 Real Output JESD204B fOUT / 4 2 fOUT / 4 fOUT / 4 LPF LPF 2 LPF LPF N/2 2 LPF LPF IQ Data Real[ ] Real[ ] Real[ ] IQ Data IQ Data 32 ADC32RF44 SBAS809A – FEBRUARY 2017 – REVISED MARCH 2017 www.ti.com Product Folder Links: ADC32RF44 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated 9.3.4.1 Operating Mode: Receiver In receiver mode, the DDC block can be configured to single- or dual-band operation, as shown in Figure 72. Both DDC chains use the same decimation filter setting and the available options are discussed in the Decimation Filters section. The decimation filter setting also directly affects the interface rate and number of lanes of the JESD204B interface. NOTE: Red traces show SYSREF going to the NCO blocks. Figure 72. Decimation Filter Option for Single- or Dual-Band Operation |
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