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ADS1601IPFBT 数据表(PDF) 8 Page - Texas Instruments

部件名 ADS1601IPFBT
功能描述  16-Bit, 1.25MSPS Analog-to-Digital Converter
PDF  31 Pages
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制造商  TI2 [Texas Instruments]
网页  https://www.ti.com
标志 TI2 - Texas Instruments

ADS1601IPFBT 数据表(HTML) 8 Page - Texas Instruments

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CLK
SYNC
t
SSC
t
HSC
FSO
t
C
t
SYPW
t
STL
CLK
FSO
t
CPW
SCLK
t
CS
t
CF
t
FPW
DOUT
t
DS
t
DH
MSB
BIT
14
LSB
NewData
BIT
1
t
CPW
ADS1601
SBAS322D
– DECEMBER 2004 – REVISED OCTOBER 2011
www.ti.com
TIMING DIAGRAMS
Figure 1. Initialization Timing
TIMING REQUIREMENTS
For TA = –40°C to +85°C, DVDD = 2.7V to 3.6V, and IOVDD = 2.7V to 5.25V.
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNIT
tSYPW
SYNC positive pulse width
1
CLK period
tC
Clock period (CLK)
50
ns
tSSC
Setup time; SYNC rising edge to CLK rising edge
0.5
CLK period
tHSC
Hold time; CLK rising edge to SYNC falling edge
0.5
CLK period
Settling time of the ADS1601; FSO falling edge to next
tSTL
833
CLK periods
FSO rising edge
Figure 2. Data Retrieval Timing
TIMING REQUIREMENTS
For TA = –40°C to +85°C, DVDD = 2.7V to 3.6V, and IOVDD = 2.7V to 5.25V.
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNIT
tCS
Rising edge of CLK to rising edge of SCLK
15
ns
tCF
Rising edge of SCLK to rising edge of FSO
5
ns
tCPW
CLK positive or negative pulse width
25
ns
tFPW
Frame sync output high pulse width
1
CLK period
tDS
SCLK rising edge to new DOUT valid
5
ns
tDH
SCLK falling edge to DOUT invalid
20
ns
8
Copyright
© 2004–2011, Texas Instruments Incorporated



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