N

CLK

D

OVR

[11:0],

N+1

N+5

t

CLKL

t

DRY

t

DATA

t

CLKH

t

a

D[11:0], OVR

CLK

N+2

N+3

N+4

DRY

DRY

(1)

N

N+1

N – 1

Sample

N – 1

T0158-01

Latency = 3.5 Clock Cycles

ADS5463

ADS54RF63

www.ti.com ................................................................................................................................................... SLAS515E – NOVEMBER 2006 – REVISED JULY 2009

ELECTRICAL CHARACTERISTICS (continued)

Typical values at TA = 25°C, minimum and maximum values over full temperature range TMIN = –40°C to TMAX = 85°C,

ADS5463 sampling rate = 500 MSPS, ADS54RF63 sampling rate = 550 MSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3

= 3.3 V, DVDD3 = 3.3 V, –1-dBFS differential input, and 3-VPP differential clock, unless otherwise noted

ADS54RF63

ADS5463

PARAMETER

TEST CONDITIONS

UNIT

MIN

TYP

MAX

MIN

TYP

MAX

Two-Tone SFDR

fIN1 = 65 MHz, fIN2 = 70 MHz,

90

90

each tone at –7 dBFS

fIN1 = 65 MHz, fIN2 = 70 MHz,

90

89

each tone at –16 dBFS

fS = 500MSPS

fIN1 = 350 MHz, fIN2 = 355 MHz,

90

82

each tone at –7 dBFS

2-tone

dBFS

SFDR

fIN1 = 350 MHz, fIN2 = 355 MHz,

90

89

each tone at –16 dBFS

fIN1 = 397.5 MHz, fIN2 = 402.5

NA

90

MHz, each tone at –7 dBFS

fS = 550MSPS

fIN1 = 647.5 MHz, fIN2 = 652.5

NA

84

MHz, each tone at –7 dBFS

LVDS DIGITAL OUTPUTS

Differential output

VOD

247

350

454

247

350

454

mV

voltage (±)

Common-mode

VOC

1.125

1.375

1.125

1.375

V

output voltage

(1)

Polarity of DRY is undetermined. For further information, see the Digital Outputs section.

Figure 1. Timing Diagram

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