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TSL6801 数据表(PDF) 6 Page - STMicroelectronics |
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TSL6801 数据表(HTML) 6 Page - STMicroelectronics |
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6 / 20 page ![]() 3 Electrical characteristics Table 6. Electrical characteristics at VCC = 1.8 V to 5 V, VICM = VOUT = VCC / 2, T = 25 °C and OUT connected to VCC / 2 through RL=10 kΩ (unless otherwise specified). Production screening at VCC = 5 V, operation on the full supply range ensured by design and characterizat ion. Symbol Parameter Conditions Min. Typ. Max. Unit DC performance Vio Input offset voltage ± 0.1 ± 3 mV ∆Vio/DT Input offset voltage temperature drift -40 °C ≤ T ≤ 85 °C ±2 µV/°C Iib Input bias current ±1 pA Iio Input offset current ±1 pA AVD Open loop gain VCC-+300 mV ≤ VOUT ≤ VCC+-300 mV, RL = 100 kΩ 95 115 dB CMR Common-mode rejection ratio 20.log (ΔVio/ΔVicm) VCC-≤ Vicm ≤ VCC+ 60 80 dB VOH High level output voltage drop (VOH=VCC+-VOUT) 40 mV VOL Low level output voltage drop (VOL=VOUT) 40 mV IOUT Short-circuit current VCC+ = 1.8 V ±5 mA VCC+ = 5 V ±10 ICC Supply current (by operational amplifier) 0.6 1 µA AC performance GBP Gain bandwidth product CL = 60 pF 8 kHz SR Slew rate CL = 60 pF, AV=1 V/V, 10% to 90% 3 V/ms Φm Phase margin CL = 60 pF 50 Degrees en Input voltage noise density f = 100 kHz 240 nV/√Hz f = 1 kHz 225 en p-p Input noise voltage 0.1 Hz ≤ f ≤ 10 Hz 8 µVpp TSL6801, TSL6802, TSL6804 Electrical characteristics DS13726 - Rev 3 page 6/20 |
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