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ADS7253 数据表(PDF) 11 Page - Texas Instruments

部件名 ADS7253
功能描述  ADSxx53 Dual, High-Speed, 16-, 14-, and 12-Bit, Simultaneous-Sampling, Analog-to-Digital Converters
PDF  75 Pages
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制造商  TI2 [Texas Instruments]
网页  https://www.ti.com
标志 TI2 - Texas Instruments

ADS7253 数据表(HTML) 11 Page - Texas Instruments

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ADS8353, ADS7853, ADS7253
www.ti.com
SBAS584B – OCTOBER 2013 – REVISED AUGUST 2014
7.9 Timing Requirements: Interface Mode
(1)
PARAMETER
ASSOCIATED FIGURES
tCLK
CLOCK period
Figure 1, Figure 91, Figure 92, Figure 93, Figure 94
tACQ
Acquisition time
Figure 91, Figure 92, Figure 93, Figure 94
tCONV
Conversion time
Figure 91, Figure 92, Figure 93, Figure 94
(1)
These parameters are specific to the interface mode of operation. Refer to the Conversion Data Read section for more details.
7.10 Timing Characteristics: Serial Interface
PARAMETER
TEST CONDITIONS
ASSOCIATED FIGURES
MIN
TYP
MAX
UNIT
TIMING REQUIREMENTS
tPH_CK
CLOCK high time
0.4
0.6
tCLK
tPL_CK
CLOCK low time
Figure 1
0.4
0.6
tCLK
fCLK
CLOCK frequency
1 / tCLK
MHz
tPH_CS
CS high time
Figure 1
40
ns
ADS8353
150
ns
tPH_CS_SHRT
CS high time after frame abort
ADS7853
Figure 99
100
ns
ADS7253
70
ns
Setup time: CS falling edge to
tSU_CSCK
15
ns
SCLK falling edge
Delay time: Last SCLK falling edge
tD_CKCS
15
ns
to CS rising edge
Figure 1
Setup time: DIN data valid to SCLK
tSU_CKDI
5
ns
falling edge
Hold time: SCLK falling edge to
tHT_CKDI
5
ns
(previous) data valid on DIN
Power-up time from STANDBY
tPU_STDBY
Figure 96
1
µs
mode
With internal reference
3
ms
tPU_SPD
Power-up time from SPD mode
Figure 98
With external reference
1
ms
TIMING SPECIFICATIONS
ADS8353
32-CLK mode
1.666
µs
Figure 91, Figure 92
32-CLK mode
1
µs
ADS7853
tTHROUGHPUT
Throughput time
16-CLK mode
Figure 93, Figure 94
1
µs
32-CLK mode
Figure 91, Figure 92
1
µs
ADS7253
16-CLK mode
Figure 93, Figure 94
1
µs
Figure 91, Figure 92,
fTHROUGHPUT
Throughput
1 / tTHROUGHPUT kSPS
Figure 93, Figure 94
Delay time: CS falling edge to data
tDV_CSDO
12
ns
enable
Delay time: CS rising edge to data
tDZ_CSDO
Figure 1
12
ns
going to 3-state
Delay time: SCLK falling edge to
tD_CKDO
20
ns
next data valid
Copyright © 2013–2014, Texas Instruments Incorporated
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Product Folder Links: ADS8353 ADS7853 ADS7253



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