3.5

Test circuit

Figure 3. Test circuit stereo application and mono BTL mode

GAIN SETTING

GAIN

JUMPER

23.6dB

29.6dB

33.1dB

35.6dB

J9

J10

J11

J12

Optional components or circuitry

L+

R+

R-

VCC

GND

L+

L-

R+

R-

TDA7498E

MUTE

STBY

3V3 POWER SUPPLY

Single-Ended

Input

CLASS-D AMPLIFIER

For Single-Ended

Input and

Load=4 ohm

For

LOUTPUT

INPUT

L-

MONO

OUT

FREQUENCY SHIFT

Load=4 ohm

R-OUTPUT

MONO

OUT

(PSSO36)

MONO Config

MONO

Config

MONO

INPUT

L+, L- Only

MODE SETTING

STEREO

MONO

MODE

JUMPER

J5

J6,J3,J8

C5

100nF

L4

C1

1uF

C2

1uF

C11

1uF

C12

1uF

C25

100nF

C19

100nF

C27

330pF

R6

22R

C40

220nF

C41

220nF

C21

330pF

R5

22R

C42

220nF

C43

220nF

C3

1nF

C4

1nF

C13

1nF

C14

1nF

32

INPB

36 VSS

9

OUTNB

5

PGNDB

7

PVCCB

3

OUTPB

10

OUTNA

12

PVCCA

14

PGNDA

16

OUTPA

33

INNB

8

OUTNB

4

PGNDB

21 MUTE

6

PVCCB

2

OUTPB

29

SVR

11

OUTNA

1

SUB_GND

22 INPA

23

INNA

27 SGND

26

VDDS

28

DIAG

19

VDDPW

18 PGND

20

STBY

24

ROSC

31 MODE

35 SVCC

30 GAIN

25

SYNCLK

17

OUTPA

15

PGNDA

34

VREF

13

PVCCA

IC1

TDA7498E

R1

47k

R7

22R

C6

100nF

R4

120k

R2

33k

R8

6.8k

C26

1uF

C10

100nF

C20

1uF

J6

J9

2

1

3

S1

2

1

3

S2

C9

100nF

C29

2.2uF

2

GND

1

OUT

3

IN

IC2

L4931CZ33

+ C15

2.2uF

16V

1

2

J2

J8

J7

+ C7

2.2uF

16V

+

C23

2200uF

50V

L3

L1

L2

C17

10uF

10V

C16

10uF

10V

D1

18V

J4

C30

1uF

C31

1uF

R15

8R

C28

220nF

R16

8R

C24

220nF

R17

8R

C18

220nF

R18

8R

C22

220nF

SYNC

2

4

1

3

J1

R10

100k

R11

100k

R12

100k

J11

J12

J5

J10

J3

R3

39K

C8

100nF

R9

180K

1

2

3

Q1

KTC3875(S)

R13

47k

R14

100k

D2

D3

D4

D8

D6

D5

D7

D9

+

C32

2200uF

50V

1

2

J14

1

2

J13

WL+

WR+

WL-

WR-

L1S

L2S

L3S

L4S

R19

33k

DIAG

VDDS

VDDS

VDDS

VCC

VCC

VCC

VCC

VCC

VDDS

3V3

PS

PS

TDA7498E

Test circuit

DS8807 - Rev 4

page 7/17