Input stage

The input stage has a fail-safe architecture, effectively allowing bias voltages higher than VCC. This is especially

useful if the comparator is disconnected from the power supply (VCC = 0 V). Care must be taken when VIN

exceeds VCC. Keep slew rates below 0.5 V/µs to prevent false triggering of the ESD clamp.

Figure 52. Input stage

+

–

V+

IN+

IN–

V-

Output stage

With a dedicated ESD clamp in the open-drain output stage, voltage levels higher than VCC can be applied to the

comparator output. The TS3121 can thus be used for level shifter applications where the output voltage is

independent of the comparator supply voltage.

Figure 53. Output stage

+

–

OUT

V-

PCB layout recommendations

Particular attention must be paid to the layout of the PCB tracks connected to the comparator, load, and power

supply. The power and ground traces are critical as they must provide adequate energy and grounding for all

circuits. The best practice is to use short and wide PCB traces to minimize voltage drops and parasitic

inductance. In addition to minimizing parasitic impedance over the entire surface, a multi-via technique that

connects the bottom and top layer ground planes together in many locations is often used. The copper traces that

connect the output pins to the load and supply pins should be as wide as possible to minimize trace impedance.

Decoupling capacitor

To ensure op amp full functionality, it is recommended to place two decoupling capacitors of 100 nF and 10 nF as

close as possible to the comparator supply pins. A good decoupling helps to reduce electromagnetic interference

impact.

TS3121, TS3121A

Application information

DS14484 - Rev 3

page 23/34