Figure 45.

High-to-low propagation delay vs. input common-mode voltage at VCC = 5.0 V, CL = 15 pF, RPU = 2.5 kΩ, VPU =

VCC........................................................................... 18

Figure 46.

High-to-low propagation delay vs. supply voltage at Vicm = VCC/2, CL = 15 pF, RPU = 2.5 kΩ, VPU = VCC ..... 19

Figure 47.

Functional block diagram ............................................................ 20

Figure 48.

Rise time vs. pull-up resistor.......................................................... 21

Figure 49.

Fail-safe bias current vs. voltage....................................................... 21

Figure 50.

Turn-on timing diagram ............................................................. 22

Figure 51.

Propagation delay ................................................................. 22

Figure 52.

Input stage...................................................................... 23

Figure 53.

Output stage .................................................................... 23

Figure 54.

Typical application schematic ......................................................... 24

Figure 55.

SC70-5 (or SOT323-5) package outline .................................................. 26

Figure 56.

SOT23-5 package outline ........................................................... 27

TS3121, TS3121A

List of figures

DS14484 - Rev 3

page 33/34