List of figures

Figure 1.

Pin connections (top view) ............................................................ 2

Figure 2.

Block diagram .................................................................... 3

Figure 3.

Input offset voltage production distribution ................................................. 7

Figure 4.

Input offset voltage vs. temperature...................................................... 7

Figure 5.

Common-mode rejection ratio production distribution.......................................... 7

Figure 6.

Common mode rejection ratio vs. temperature .............................................. 7

Figure 7.

Gain vs. frequency ................................................................. 7

Figure 8.

Power supply rejection ratio vs. frequency ................................................. 7

Figure 9.

Common mode rejection ratio vs. frequency ................................................ 8

Figure 10.

Positive output voltage swing vs. output current VCC = 2.7 V .................................... 8

Figure 11.

Negative output voltage swing vs. output current VCC = 2.7 V .................................... 8

Figure 12.

Positive output voltage swing vs. output current VCC = 5 V ...................................... 8

Figure 13.

Negative output voltage swing vs. output current VCC = 5 V ..................................... 8

Figure 14.

Positive output voltage swing vs. output current VCC = 26 V ..................................... 8

Figure 15.

Negative output voltage swing vs. output current VCC = 26 V .................................... 9

Figure 16.

Input bias current vs. input common mode voltage with supply voltage = 5 V ......................... 9

Figure 17.

Input bias current vs. input common mode voltage with supply voltage = 0 V ......................... 9

Figure 18.

Input bias current vs. temperature ....................................................... 9

Figure 19.

Quiescent current vs. temperature....................................................... 9

Figure 20.

Input referred noise vs. frequency ....................................................... 9

Figure 21.

0.1 Hz to 10 Hz voltage noise (referred to input) ............................................ 10

Figure 22.

Step response (10-mVpp input step) .................................................... 10

Figure 23.

Common mode voltage transient response................................................ 10

Figure 24.

Inverting differential input overloaded ................................................... 10

Figure 25.

Non inverting differential input overload .................................................. 10

Figure 26.

Start-up response ................................................................. 10

Figure 27.

Brownout recovery ................................................................ 11

Figure 28.

Power supply when Vicm > 2.5 V ....................................................... 12

Figure 29.

Input bias current vs. common mode voltage Vcc = 5 V ....................................... 13

Figure 30.

Vref powered by an external voltage source with a TSC210 .................................... 13

Figure 31.

Output reference to ground .......................................................... 14

Figure 32.

Output reference to Vcc ............................................................. 14

Figure 33.

External supply................................................................... 15

Figure 34.

Shunt resistor value trade-off (TSC213) .................................................. 16

Figure 35.

Input current..................................................................... 18

Figure 36.

Capacitive load response at Vcc = 3.3 V.................................................. 19

Figure 37.

Capacitive load response at Vcc = 3.3 V with a step of 100 mV .................................. 20

Figure 38.

RC filter when driving ADC........................................................... 20

Figure 39.

Capacitive load response at Vcc = 3.3 V with 260 kHz RC filter .................................. 21

Figure 40.

Capacitive load response at Vcc = 3.3 V with 260 kHz RC filter and Rl = 10 kΩ ....................... 21

Figure 41.

Stability criteria with a serial resistor at Vcc = 5 V............................................ 21

Figure 42.

Stability criteria with a serial resistor and a Rload = 10 kΩ at Vcc = 5 V ............................. 21

Figure 43.

ADC in differential mode ............................................................ 22

Figure 44.

Recommended layout .............................................................. 23

Figure 45.

EMIRR on pin+ ................................................................... 23

Figure 46.

EMIRR on pin- ................................................................... 23

Figure 47.

Input filtering .................................................................... 24

Figure 48.

TSC212 with input differential voltage ................................................... 25

Figure 49.

Power supply monitoring and OCP function ............................................... 26

Figure 50.

SC70-6 package outline............................................................. 27

Figure 51.

SC70-6 recommended footprint ....................................................... 28

TSC210, TSC211, TSC212, TSC213, TSC214, TSC215

List of figures

DS13237 - Rev 7

page 36/38