STA529 datasheet(21/57 Pages) STMICROELECTRONICS

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STA529

PLL

Doc ID 13095 Rev 3

21/57

Input frequency divider

This frequency divider divides the PLL input clock CLKIN by a factor called the input division

factor (IDF) to generate the PFD input frequency INFIN.

Loop frequency divider

This frequency divider is present within the PLL for dividing fVCO by a factor called the loop

division factor (LDF). The output of this block is clock FBCLK.

Output frequency divider

The output frequency divider divides fVCO by the output division factor (ODF) to produce the

output clock PHI and the clock to the core. In the STA529, ODF = 2 and cannot be

reconfigured.

Lock-detect circuit

The output of this block (signal LOCKP) is asserted high when the PLL enters the state of

Coarse Lock in which the output frequency is within ±10%, approximately, of the desired

frequency. LOCKP is refreshed every 32 cycles of clock INFIN. The generated value is

based on the result of comparing the number of FBCLK cycles in a window of 14 INFIN

cycles. The different cases generated after comparison are as follows.

●

If LOCKP is already at 0, then in the next refresh cycle LOCKP goes to 1 if the number

of FBCLK cycles in the 14-cycle INFIN window is 13, 14, or 15. Otherwise LOCKP

stays at 0.

●

If LOCKP is already at 1, then in the next refresh cycle LOCKP goes to 0 if the number

of FBCLK cycles in the 25-cycle INFIN window is less than 11 or higher than 17,

otherwise LOCKP stays at 1.

●

If LOCKP is already at 1 and CLKIN is lost (no longer present on the input pin), LOCKP

stays at 1. In this case, the PLL is unlocked.

PLL filter

Figure 6 below shows the PLL filter circuit. Recommended values are R1 = 12.5 k

Ω,

C1 = 250 pF and C2 = 82 pF.

Figure 6.

PLL filter circuit

Table 12 on page 16 gives a typical lock time value for the PLL.

Ground

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