STA529Q datasheet(22/57 Pages) STMICROELECTRONICS

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PLL

STA529

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Doc ID 13095 Rev 3

6.2

Configuration examples

The STA529 PLL can be configured in two ways:

●

default startup configuration

●

direct PLL programming

The default startup configuration reads the device defaults. With this configuration, it is not

necessary to program the PLL dividers directly as preset values are used. In this mode, the

oversampling ratio between pins XTI (or MCLK33) and LRCLKI is fixed to 256.

The direct PLL programming bypasses the automatic presets allowing direct programming

of the PLL dividers.

The output PLL frequency can be determined by the following equations.

Output division factor:

ODF = 2.

Relation between input and output clock frequency:

fINFIN = fXTI / IDF.

If register bit PLLCFG0.FRAC_CTRL = 1

fVCO = fINFIN * (LDF + FRACT / 2

16 + 1 / 217)

fPHI = fVCO / ODF.

When register bit PLLCFG0.DITHER_DISABLE[1] = 1, the 1/217 factor is not in the

multiplication. This is recommended in order to keep register bit

PLLCFG0.DITHER_DISABLE[1] = 0, otherwise there can be spurious signals in the output

clock spectrum.

If register bit PLLCFG0.FRAC_CTRL = 0, then:

fVCO = fINFIN * LDF

fPHI = fVCO / ODF.

In the above equations:

FRACT = decimal equivalent of register bit PLLCFG1.FRAC_INPUT[15:0]

IDF = input division factor

LDF = loop division factor

ODF = output division factor = 2

fINFIN = INFIN frequency

fXTI = XTI frequency

fVCO = VCO frequency

fPHI = frequency of the PLL output clock.

When selecting the values for IDF, LDF and FRACT, ensure that the following limits are

maintained:

2.048 MHz < fXTI < 49.152 MHz

2.048 MHz < fINFIN < 16.384 MHz

65.536 MHz < fVCO < 98.304 MHz

There are also some additional constraints on IDF and LDF. IDF should be greater than 0,

LDF should be greater than 5 if FRAC_CTRL = 0 and greater than 8 if FRAC_CTRL = 1.

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