STAMP0 datasheet(23/62 Pages) STMICROELECTRONICS

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STAMP0

Architecture

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Figure 13: Channel mapping scheme

The mapping between the input streams and the frame output slots is flexible and can be

configured using the Channel Selector (CSx in Figure 13: "Channel mapping scheme")

through the I²C registers (Reg. 0xA, Reg. 0xB, Reg. 0xC and Reg. 0xD). Moreover each

CSx has an extra input “ALL0” employed to set to zero the content of the slots that are not

used (empty bits) in the frame out.

In each slot, audio data is arranged by the most significant bit (MSB) first, high byte first.

The frame output is selected using the SCK_SLOT signal whose value is determined by

combining the SCK rate and the slot size.

However the default SCK_RATE is equal to 128xFs, the slot size is equal to 16 bits and the

CH1 is mapped to the Slot1, the CH2 is mapped to the Slot2 and so on.

4.5.2

Time division multiplexing

Time-division multiplexing (TDM) is a method of putting multiple data streams in one data

signal by separating the signal into many segments.

The TDM hardware interface has three signals, serial clock (SCK pin in Figure 12: "Serial

output interface architecture"), frame sync (FS=FSY pin in Figure 12: "Serial output

interface architecture") and data (TDM pin in Figure 12: "Serial output interface

architecture").

The TDM and the FSY signals can change on the falling edges of the SCK and are valid on

the rising edge of SCK (Figure 14: "Data and FSY change on the falling edges of SCK and

are valid on the rising edges of SCK. The frame starts on the rising edge of FSY (NO

DELAY)" and Figure 16: "Data and FSY change on the falling edges of SCK and are valid

on the rising edges of SCK.The frame starts on the falling edge of FSY (NO DELAY)") or

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STAMP0 数据表(PDF) 23 Page - STMicroelectronics