DocID006317 Rev 5

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TDA7449

I2C bus interface

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4

I2C bus interface

Data transmission from the microprocessor to the TDA7449 and vice versa takes place

through the 2-wire I2C bus interface, consisting of the two lines SDA and SCL (pull-up

resistors to the positive supply voltage must be connected).

4.1

Data validity

As shown in Figure 10, the data on the SDA line must be stable during the high period of the

clock. The HIGH and LOW state of the data line can only change when the clock signal on

the SCL line is LOW.

4.2

Start and stop conditions

As shown in Figure 11, a start condition is a HIGH-to-LOW transition of the SDA line while

SCL is HIGH. The stop condition is a LOW-to-HIGH transition of the SDA line while SCL is

HIGH.

4.3

Byte format

Every byte transferred on the SDA line must contain 8 bits. Each byte must be followed by

an acknowledge bit. The MSB is transferred first.

4.4

Acknowledge

The master (μP) puts a resistive HIGH level on the SDA line during the acknowledge clock

pulse (see Figure 12). The peripheral (audio processor) that acknowledges has to pull down

(LOW) the SDA line during this clock pulse.

The audio processor which has been addressed has to generate an acknowledge after the

reception of each byte, otherwise the SDA line remains at the HIGH level during the ninth

clock pulse time. In this case the master transmitter can generate the STOP information in

order to abort the transfer.

4.5

Transmission without acknowledge

Instead of detecting the acknowledge from the audio processor, the μP can use a simpler

transmission which is to simply wait one clock pulse without checking the slave

acknowledge and send the new data.

This is of course a riskier approach.

Obsolete

Product(s)

- Obsolete

Product(s)