STM32WL33C8 datasheet(21/91 Pages) STMICROELECTRONICS

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3.10

General purpose inputs/outputs (GPIO)

Each general-purpose I/O port has four 32-bit configuration registers, two 32-bit data registers, and a 32-bit set/

reset register. In addition, all GPIOs have a 32-bit locking register and two 32-bit alternate function selection

registers.

Each of the GPIO pins can be configured by software:

•

Output states: push-pull or open drain + pull-up/down

•

Output data from output data register or peripheral (alternate function output)

•

Speed selection for each I/O

•

Input states: floating, pull-up/down, analog

•

Input data to input data register or peripheral (alternate function input)

•

Bit set and reset register for bitwise write access

•

Locking mechanism provided to freeze the I/O port configurations

•

Analog function

•

Alternate function selection registers

•

Fast toggle capable of changing every clock cycle

•

Highly flexible pin multiplexing allows the use of I/O pins as GPIOs or as one of several peripheral

functions.

3.11

Direct memory access (DMA)

Direct memory access (DMA) provides high-speed data transfer between peripherals and memory as well as

memory to memory. Data can be quickly moved by DMA without any CPU actions. This keeps CPU resources

free for other operations. The implemented DMA has an arbiter for handling the priority between DMA requests.

The DMA main features are as follows:

•

Eight independently configurable channels (requests)

•

Each of the eight channels is connected to dedicated hardware DMA requests, software trigger is also

supported on each channel. This configuration is done by software

•

Priorities between requests from channels of the DMA are software programmable (4 levels consisting of

very high, high, medium, low) or hardware in case of equality (request 1 has priority over request 2, and so

on.)

•

Independent source and destination transfer size (byte, half word, word), emulating packing and

unpacking. Source/destination addresses must be aligned on the data size

•

Support for circular buffer management

•

event flags (DMA Half Transfer, DMA Transfer complete and DMA Transfer Error) logically ORed together

in a single interrupt request for each channel

•

Memory-to-memory transfer (SRAM0/SRAM1)

•

Peripheral-to-memory and memory-to-peripheral, and peripheral-to-peripheral transfers

•

Access to SRAMs, APB0 and APB1 peripherals as source and destination

•

Programmable number of data to be transferred: up to 65536

3.12

Nested vectored interrupt controller (NVIC)

The interrupts are handled by the Cortex-M0+ Nested Vector Interrupt Controller (NVIC). The NVIC controls

specific Cortex-M0+ interrupts (address 0x00 to 0x3C) as well as 32 user interrupts (address 0x40 to 0xBC). In

the STM32WL33xx device, the user interrupts have been connected to the interrupt signals of the different

peripherals (GPIO, flash controller, timer, USART, and so on). These interrupts can be controlled using the ISER,

ICER, ISPR and ICOR registers (see “Cortex-M0+ Devices Generic User Guide”).

STM32WL33xx

Functional overview

DS14221 - Rev 5

page 21/91

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