0

1

2

3

0

20

40

60

80

100

120

140

160

180

I

= C

* V

* f

dyn

PD

DD

V

= 2.5 V

DD

f - Clock Frequency - MHz

0

5

10

15

0

20

40

60

80

100

120

140

160

180

V

= 2.5 V

DD

P

+ P

dyn

Cload8pF

P

+ P

dyn

Cload50/2

P

+ P

dyn

Cload2pF

f - Clock Frequency - MHz

7

CDCLVC1102, CDCLVC1103, CDCLVC1104

CDCLVC1106, CDCLVC1108, CDCLVC1110, CDCLVC1112

www.ti.com

SCAS895B – MAY 2010 – REVISED FEBRUARY 2017

Product Folder Links: CDCLVC1102 CDCLVC1103 CDCLVC1104 CDCLVC1106 CDCLVC1108 CDCLVC1110

CDCLVC1112

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Copyright © 2010–2017, Texas Instruments Incorporated

(1)

tsk(p) depends on output rise- and fall-time (tr/tf). The output duty-cycle can be calculated: odc = (tw(OUT) ± tsk(p))/tperiod; tw(OUT) is pulse-

width of output waveform and tperiod is 1/fOUT.

(2)

Parameter is specified by characterization. Not tested in production.

6.6 Switching Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

OUTPUT PARAMETERS FOR VDD = 3.3 V ± 0.3 V

tPLH, tPHL

Propagation delay

CLKIN to Yn

0.8

2.0

ns

tsk(o)

Output skew

Equal load of each output

50

ps

tr/tf

Rise and fall time

20%–80% (VOH - VOL)

0.3

0.8

ns

tDIS

Output disable time

1G to Yn

6

ns

tEN

Output enable time

1G to Yn

6

ns

tsk(p)

Pulse skew ;

tPLH(Yn) – tPHL(Yn)

(1)

To be measured with input duty

cycle of 50%

180

ps

tsk(pp)

Part-to-part skew

Under equal operating conditions for

two parts

0.5

ns

tjitter

Additive jitter rms(2)

12 kHz to 20 MHz, fOUT = 250 MHz

100

fs

OUTPUT PARAMETERS FOR VDD = 2.5 V ± 0.2 V

tPLH, tPHL

Propagation delay

CLKIN to Yn

1

2.6

ns

tsk(o)

Output skew

Equal load of each output

50

ps

tr/tf

Rise and fall time

20%–80% reference point

0.3

1.2

ns

tDIS

Output disable time

1G to Yn

10

ns

tEN

Output enable time

1G to Yn

10

ns

tsk(p)

Pulse skew ;

tPLH(Yn) – tPHL(Yn)

(1)

To be measured with input duty

cycle of 50%

220

ps

tsk(pp)

Part-to-part skew

Under equal operating conditions for

two parts

1.2

ns

tjitter

Additive jitter rms(2)

12 kHz to 20 MHz, fOUT = 180 MHz

350

fs

6.7 Typical Characteristics

Figure 1. Device Power Consumption vs Clock Frequency

(Load 50 Ω into VDD/2; 2 pF, 8 pF; Per Output)

Figure 2. Dynamic Supply Current vs Clock Frequency

(CPD = 4.5 pF, No Load; Per Output)