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DAC7750IPWPR.B 数据表(PDF) 9 Page - Texas Instruments

部件名 DAC7750IPWPR.B
功能描述  DACx750 Single-Channel, 12-Bit and 16-Bit Programmable Current Output Digital-to-Analog Converters for 4-mA to 20-mA Current-Loop Applications
PDF  56 Pages
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制造商  TI2 [Texas Instruments]
网页  https://www.ti.com
标志 TI2 - Texas Instruments

DAC7750IPWPR.B 数据表(HTML) 9 Page - Texas Instruments

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(3)
For 0-mA to 20-mA and 0-mA to 24-mA ranges, INL is calculated beginning from code 0x0100 for DAC8750 and from code 0x0010 for
DAC7750.
(4)
Loop compliance voltage is defined as the voltage at the IOUT pin.
(5)
For stability, use slew rate limit feature or add a capacitor between IOUT and GND
7.6 Electrical Characteristics: AC
At AVDD = 10 V to 36 V, GND = 0 V, REFIN= 5 V external and DVDD = 2.7 V to 5.5 V. For IOUT, RL = 300 Ω. All
specifications –40°C to 125°C (unless otherwise noted). Typical specifications are at 25°C.
PARAMETER(1)
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DYNAMIC PERFORMANCE
Output current settling time
16-mA step, to 0.1% FSR, no L (inductance)
10
μs
16-mA step, to 0.1% FSR, L < 1 mH
25
μs
AC PSRR
200-mV, 50-Hz or 60-Hz sine wave superimposed
on power-supply voltage
–75
dB
(1)
Specified by characterization, not production tested.
7.7 Timing Requirements: Write Mode
at TA = –40°C to 125°C and DVDD = 2.7 V to 5.5 V (unless otherwise noted)(1)
MIN
MAX
UNIT
t1
SCLK cycle time
33
ns
t2
SCLK low time
13
ns
t3
SCLK high time
13
ns
t4
LATCH delay time
13
ns
t5
LATCH high time(2)
40
ns
t6
Data setup time
5
ns
t7
Data hold time
7
ns
t8
LATCH low time
40
ns
t9
CLR pulse duration
20
ns
t10
CLR activation time
5
µs
(1)
Specified by design, not production tested.
(2)
Based on digital interface circuitry only. When writing to DAC control and configuration registers, consider the analog output
specifications in Section 7.6.
7.8 Timing Requirements: Readback Mode
at TA = –40°C to 125°C and DVDD = 2.7 V to 5.5 V (unless otherwise noted)(1)
MIN
MAX
UNIT
t11
SCLK cycle time
60
ns
t12
SCLK low time
25
ns
t13
SCLK high time
25
ns
t14
LATCH delay time
13
ns
t15
LATCH high time
40
ns
t16
Data setup time
5
ns
t17
Data hold time
7
ns
t18
LATCH low time
40
ns
t19
Serial output delay time (CL, SDO = 15 pF)
35
ns
t20
LATCH rising edge to SDO 3-state (CL, SDO = 15 pF)
35
ns
(1)
Specified by design, not production tested.
www.ti.com
DAC7750, DAC8750
SBAS538D – DECEMBER 2013 – REVISED DECEMBER 2021
Copyright © 2021 Texas Instruments Incorporated
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Product Folder Links: DAC7750 DAC8750



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