1

2

32XN

SCLK

SYNC

SDIN

32XN

Invalid/Interrupted Write Sequence

Output/Mode Does Not Update on the Rising SYNC

Valid Write Sequence

Output/Mode Does Update on the Rising SYNC

22

DAC80004, DAC70004, DAC60004

SLASED6D – APRIL 2016 – REVISED DECEMBER 2017

www.ti.com

Product Folder Links: DAC80004 DAC70004 DAC60004

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Copyright © 2016–2017, Texas Instruments Incorporated

Device Functional Modes (continued)

Figure 56. SYNC Interrupt – Daisy-Chain Operation

8.4.2 SPI Shift Register

The SPI shift register is 32 bits wide, as shown in Table 2. The shift register command mapping is shown in

Table 3. The DACx0004 accepts DAC code in straight binary format. Note that, the DAC data is left alligned from

MSB (D19) to LSB (D4 - 16 bits, D6 - 14 bits, D8 - 12 bits).

Table 2. DACx0004 SPI Shift Register Format

D31

D30

D29

D28

D27-D24

D23-D20

D19-D04

D03-D00

Don't Cares

R/W

Command Bits

Channel Address

Bits

16/14/12-Bit DAC Data left alligned/Power

Down Bits/Device Ready bit

Mode Bits

Table 3. DAC Commands

D31 - D28

D27 - D24

D23 - D20

D19 - D16

D15 - D12

D11 - D08

D07 - D04

D03 - D00

Commands

X

W/R

0

0

0

0

Channel

Address

DAC Data

DAC Data

DAC Data

DAC Data

X

Write to buffer n

X

W

0

0

0

1

Channel

Address

X

X

X

X

X

Update DAC n

X

W

0

0

1

0

Channel

Address

DAC Data

DAC Data

DAC Data

DAC Data

X

Write to buffer n and update all

DACs (Software LDAC)

X

W

0

0

1

1

Channel

Address

DAC Data

DAC Data

DAC Data

DAC Data

X

Write to buffer and update DAC

n

X

W/R

0

1

0

0

X

X

X

X

PD1

PD0

Ch-D

Ch-C

Ch-B

Ch-A

Power up/down DAC n

X

W/R

0

1

0

1

X

X

X

X

X

X

X

CM1

CM0

Clear mode register

X

W/R

0

1

1

0

X

X

X

X

X

Ch-D

Ch-C

Ch-B

Ch-A

LDAC register

X

W

0

1

1

1

X

X

X

X

X

X

Software reset

X

W/R

1

0

0

0

X

X

X

X

X

X

DSD

0

X

Disable SDO register

X

X

1

0

0

1

X

X

X

X

X

X

Reserved

X

W/R

1

0

1

0

X

X

X

X

X

Ch-D

Ch-C

Ch-B

Ch-A

Short circuit limit register

X

W

1

0

1

1

X

X

X

X

X

X

Software clear

X

X

1

1

0

0

X

X

X

X

X

X

Reserved

X

R

1

1

0

1

X

X

X

X

X

DRDY

X

Status register

X

W

1

1

1

0

X

X

X

X

X

X

No operation (NOP)

X

X

1

1

1

1

X

X

X

X

X

X

Reserved

Table 4. Channel Address Bits

CHANNEL ADDRESS BITS

DESCRIPTION

D23

D22

D21

D20

0

0

0

0

Select channel A

0

0

0

1

Select channel B

0

0

1

0

Select channel C

0

0

1

1

Select channel D

1

1

1

1

Select all channel