Electrical performance characteristics

L9733

16/35

DocID11319 Rev 12

3.3

SPI characteristics and timings

Tamb= -40 to 125 °C, Vdd = 4.5 to 5.5 Vdc, Vbat = 4.5 to 18 Vdc, unless otherwise specified

Table 8. SPI characteristics and timings

Symbol

Parameter

Conditions

Min

Typ

Max

Units

DINCin

Input capacitance

-

-

-

20

pF

SCLKCin

-

-

20

pF

DOrise

Output data (do)

rise time

50 pF from DO to Ground

See Figure 5

-

-

70

ns

DOfall

Output data (do)

fall time

See Figure 5

-

-

70

ns

DOa

Access time

See Figure 6

-

-

350

ns

DOsum

Set up time

See Figure 6

20

-

-

ns

DOhm

Hold time

See Figure 6

10

-

-

ns

DOdis

Output data (DO)

disable time

No Capacitor on DO, See Figure 5

-

-

400

ns

tthFilt

Filter time

All Fault bits are “Set”

5

-

20

s

SCLKwid

SCLK width

See Figure 5, @ fSCLK = 5.4MHz(1)

185

-

-

ns

SCLKlm

SCLK low time

See Figure 5, @ fSCLK = 5.4MHz(1)

58

-

-

ns

SCLKhm

SCLK high time

See Figure 5, @ fSCLK = 5.4MHz(1)

58

-

-

ns

SCLKrise

SCLK rise time

See Figure 5, @ fSCLK = 5.4MHz(1)

-

-

21

ns

SCLKfall

SCLK fall time

See Figure 5, @ fSCLK = 5.4MHz(1)

-

-

21

ns

CSrise

Channel select (CS)

rise time

See Figure 5 (1)

-

-

100

ns

CSfall

Channel select (CS)

fall time

See Figure 5 (1)

-

-

100

ns

CSlead

Channel select (CS)

lead time

See Figure 6 (1)

455

-

-

ns

CSlag

Channel select (CS)

lag time

See Figure 6 (1)

50

-

-

ns

DIrise

Input data (DI)

rise time

See Figure 5, @ fSCLK = 5.4MHz(1)

-

-

30

ns

DIfall

Input data (DI)

fall time

See Figure 5 @ fSCLK = 5.4MHz(1)

-

-

30

ns

DIsus

Input data (DI)

set-up time

See Figure 6, @ fSCLK = 5.4MHz(1)

15

-

-

ns

DIhs

Input data (DI)

hold time

See Figure 6, @ fSCLK = 5.4MHz(1)

10

-

-

ns

CS2SCLK

CS rise to SCLK rise

See Figure 6, @ fSCLK = 5.4MHz(1)

40

-

300

ns

1. Guaranteed by design.