L9950 datasheet(8/39 Pages) STMICROELECTRONICS

8 / 39 page

Block diagram and pin description

L9950 - L9950XP

8/39

Doc ID 10311 Rev 11

Figure 2.

Configuration diagram (top view)

PWM1

PWM1 input.

This input signal can be used to control the drivers OUT1-OUT8 and

OUT11 by an external PWM signal.

OUT7,

OUT8,

OUT9,

OUT10

Highside driver output 7,8,9,10.

The output is built by a highside switch and is intended for resistive

loads, hence the internal reverse diode from GND to the output is

missing. For ESD reason a diode to GND is present but the energy

which can be dissipated is limited. The highside driver is a power

DMOS transistor with an internal parasitic reverse diode from the

output to VS (bulk-drain-diode). The output is over-current and open

load protected.

Table 2.

Pin definitions and functions (continued)

Symbol

Function

GND 1

OUT11 2

OUT1 3

OUT2 4

OUT3 5

VS 6

VS 7

CM/PWM2 9

CSN 10

DO 11

VCC 12

CLK 13

VS 14

VS 15

OUT4 16

OUT4 17

GND 18

GND

OUT11

OUT10

OUT9

31 OUT8

PWM1

OUT6

OUT5

GND

OUT7

Power SO36

Chip

Leadframe

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