STA339BW datasheet(39/78 Pages) STMICROELECTRONICS

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STA339BW

7.5.8

Soft volume update enable

7.6

Configuration register F (addr 0x05)

7.6.1

Output configuration

Table 44. Soft volume update enable

Bit

R/W

RST

Name

Description

R/W

SVE

1: Volume adjustments ramp according to SVR settings

0: Volume adjustments occur immediately

EAPD

PWDN

ECLE

LDTE

BCLE

IDE

OCFG1

OCFG0

01011100

Table 45. Output configuration

Bit

R/W

RST

Name

Description

R/W

OCFG0

Selects the output configuration

R/W

OCFG1

Table 46. Output configuration engine selection

OCFG[1:0]

Output configuration

Config pin

2 channel (full-bridge) power, 2 channel data-out:

1A/1B

 1A/1B

2A/2B

 2A/2B

LineOut1

 3A/3B

LineOut2

 4A/4B

Line Out Configuration determined by LOC register

2(Half-Bridge).1(Full-Bridge) On-Board Power:

 1A

Binary 0 °

 1B

Binary 90°

3A/3B

 2A/2B Binary 45°

1A/B

 3A/B

Binary 0°

2A/B

 4A/B

Binary 90°

2 Channel (Full-Bridge) Power, 1 Channel FFX:

1A/1B

 1A/1B

2A/2B

 2A/2B

3A/3B

 3A/3B

EAPDEXT and TWARNEXT Active

1 Channel Mono-Parallel:

 1A/1B

w/ C3BO 45°

 2A/2B

w/ C3BO 45°

1A/1B

 3A/3B

2A/2B

 4A/4B

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