MB85RS64

DS501-00012-7v2-E

7



RDSR

The RDSR command reads status register data. After op-code of RDSR is input to SI, 8-cycle clock is input

to SCK. The SI value is invalid during this time. SO is output synchronously to a falling edge of SCK. In the

RDSR command, repeated reading of status register is enabled by sending SCK continuously before rising

of CS.



WRSR

The WRSR command writes data to the nonvolatile memory bit of status register. After performing WRSR

op-code to a SI pin, 8 bits writing data is input. WEL (Write Enable Latch) is not able to be written with WRSR

command. A SI value correspondent to bit 1 is ignored. Bit 0 of the status register is fixed to “0” and cannot

be written. The SI value corresponding to bit 0 is ignored. The WP signal level shall be fixed before performing

the WRSR command, and do not change the WP signal level until the end of command sequence.

SO

SCK

SI

CS

00000101

High-Z

7

6

5

4

3

2

1

0

Invalid

MSB

7

6

5

4

3

2

1

0

Data Out

LSB

Invalid

SO

SCK

SI

CS

00000001

7

6

5

4

3

2

1

0

Data In

MSB

7

6

5

4

3

2

1

0

High-Z

LSB

7654

3

210

Instruction