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L9305 数据表(PDF) 13 Page - STMicroelectronics |
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L9305 数据表(HTML) 13 Page - STMicroelectronics |
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13 / 107 page  4.6 Input / output electrical specifications 4.75 V ≤ VDD ≤ 5.5 V; 5.5 ≤ VBATP ≤ 19 V; -40 °C ≤ Tj ≤ 175 °C unless otherwise noted. All voltages refer to GNDA pin. Table 7. Digital input/output electrical performance Symbol Parameter Test condition Min Typ Max Unit Pin EN_DR_low Logic input low detection – – – 0.75 – EN_DR EN_DR_high Logic Input high detection – 1.75 – – V EN_DR EN_DR_hyst Input hysteresis voltage – 0.1 – – V EN_DR EN_DR_pd Inter pull down resistance VIN < 3V 10 38 70 kΩ EN_DR EN_DR_deglitch EN_DR deglitch filter Guaranteed by scan 9 12 µs EN_DR EN_DR_test_low Logic input low detection – – – 6 – EN_DR EN_DR_test_high Logic input high detection – 9 – – V EN_DR EN_DR_test_hyst Input hysteresis voltage – 0.1 – – V EN_DR INx_DISx_low Logic Input low detection – – – 0.75 V INx_DISx INx_DISx_high Logic input high detection – 1.75 – – V INx_DISx INx_DISx_hyst Input hysteresis voltage – 0.1 – – V INx_DISx INx_DISx_pd Inter pull down resistance VIN < 3V 10 38 70 kΩ INx_DISx INx_DISx_deglitch_SW Actuation deglitch in SW mode Guaranteed by scan 3 3.5 3.9 µs INx_DISx INx_DISx_deglitch_HW Disable deglitch in HW mode Guaranteed by scan 1.2 1.5 1.7 µs INx_DISx RESn_low Logic input low detection – – – 0.75 – RESn RESn_high Logic input high detection – 1.75 – – V RESn RESn_hyst Input hysteresis voltage – 0.1 – – V RESn RESn_pd Inter pull down resistance VIN < 2.5V 10 38 70 kΩ RESn RESn_deglitch RESn deglitch filter Guaranteed by scan 4.5 5 7 µs RESn FAULTn_Ileak Leakage current in tri-state condition – – – 10 – FAULTn FAULTn_low Logic low level Ext pull-up 4.7k to VDDIO – – 0.4 – FAULTn FAULTn_high Logic high level Ext pull-up 4.7k to VDDIO VDDIO-0.4 – – V FAULTn FAULTn_trise FAULTn rise time Ext pull-up 4.7k to VDDIO, Cload=20pF,tested by correlation – – 100 ns FAULTn FAULTn_tfall FAULTn fall time Ext pull-up 4.7k to VDDIO, Cload=20pF – – 100 ns FAULTn L9305 Input / Output DS12774 - Rev 10 page 13/107 |
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