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L9348

(1).See chapter 2.0 Timing Diagrams; resistive load condition; VS  9V

(2).This parameter will not be tested but assured by design

(3).Wafer-measurement

(4).Measured on P-SO36 devices

(5).Short circuit between two digital outputs (one in high the other in low state) will lead to the defined result "LOW"

IQlk

Output leakage current

VENA = L,Tj = 25°C

1

A

Tj = 125°C

5

A

VFD3/4

Forward voltage of

free wheeling diodes D3, D4

ID3/4 = -1.5A

0.5

1.75

V

RPD0

Gate pull down resistor for

nonsupplied VS

VS  0V,

VD3/4  6.5V

0.3

3

k



Timings

tON

Output ON delay time

IQ = 1A

1)

05

20

s

tf

Output ON fall time

IQ = 1A

1)

0.5

1.5

8

s

tOFF

Output OFF delay time

IQ = 1A

1)

010

30

s

tr

Output OFF rise time

IQ = 1A

1)

0.5

1.5

5

s

tDSO

Overload switch-OFF delay time

6

30

65

s

tD

Output OFF status delay time

0.75

1.5

2.25

ms

tfilter

error detection filter time

2)

5.8

35

s

tOLOFF

OLOFF error detection filter time

20

70

s

Digital Inputs (IN1 to IN4, ENA)

VIL

Input low voltage

-1.5

1

V

VIH

Input high voltage

2

6

V

VIHy

Input voltage hysteresis

2)

50

100

mV

IIN

Input pull down current

VIN = 5V, VS  6.5V

820

40

A

Digital Outputs (ST1 to ST4)

VSTL

Status output voltage in low state

5)

IST  40A

00.4

V

VSTH

Status output voltage in high state

5)

IST  -40A

2.5

3.45

V

IST  -120A

23.45

V

RDIAGL

ROUT + RDSON in low state

0.3

0.64

1.5

k



RDIAGH

ROUT + RDSON in high state

1.5

3.2

7

k



Table 5. Electrical Characteristcs

The electrical characteristics are valid within the operating range (Table 4), unless otherwise specified

Symbol

Parameter

Test Condition

Min.

Typ.

Max.

Unit